I wanted to know how that happened, going from a longstanding duopoly in the market to one with many competitors, and so I simply asked Steve.

The Other Question I asked Steve Sanghi

Some background on Steve. If you are new to the industry, you can check Google to see when he became CEO on November 18, 2024. This is actually his second stint in the role that he had held from October 1991 to March 1, 2021. On December 5, 2024, Steve joined the Intel Board of Directors.

You may recall what happened December 1-2, 2024. Pat Gelsinger, its CEO, left Intel. So Steve joined the board just days after Pat left. I asked Steve what that was like. Within the span of two weeks, he was taking over Microchip as CEO again and joining the Intel board when it had to start a CEO search.

Steve’s response was something along the lines of it being non-stop work, but he sounded very happy with how Lip-Bu Tan’s performance as Intel’s CEO thus far. Instead of pointing to a great pearl of individual fortitude, Steve was more candid, just telling me he worked a lot during that period. That type of candor was greatly appreciated.

One fun takeaway from the event was that I got a copy of Ask Steve, which has an interesting backstory as well. The book is a collection of columns Steve wrote for the Arizona Republic over the years. He answered business questions for the local publication for many years, simply as a way to teach the lessons he had accumulated.

From 2021-2024, Ganesh Moorthy was Microchip’s CEO, but he faced a pandemic-era headwind that is important to our PCIe switch story. Steve sat with maybe a dozen of us and went through Microchip’s history from the early VC days and through various acquisitions, including the Microsemi acquisition, where the PCIe switch lineage originates.

All of this context brings us back to how what was essentially a Broadcom-Microchip duopoly turned into a market where other players entered and disrupted it.

How Microchip Fell Behind in its PCIe Switches

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The drive above was tucked away in an ESD bag, not on display. It is the engineering sample for a 245.76 TB NVMe SSD that uses Sandisk’s new technology, which was also not highlighted in the company’s press release, so there is not a ton of information out there on the drive. Let us get into the vision.

The New Sandisk SSD Tech and the Trade-off

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We will post a portion of this on the STH main site later today, but I wanted to give our Substack supporters a head start and also provide a bit more on how to frame an AMD EPYC “Venice” comparison.

Where NVIDIA Vera Fits in the Data Center

One of the more interesting discussions I have had in the past 24 hours started something along the lines of “if NVIDIA wins by so much, why will it not take over every data center socket?” To be clear, NVIDIA does not even position Vera as the right CPU for that ambition.

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As some important background, I think the Qualcomm Investor Day was aimed squarely at addressing the company’s growth drivers, given an Apple business wind-down and a really tight memory market. 18 months ago, before memory prices started their sharp ascent, memory was the #1 cost item in the STH lab. The current prices are making us rethink how we operate the lab, for example, by going back to sharing modules between servers rather than buying them for each server. As a result, I tend to think of a memory-constrained environment as allocating memory to the highest-value compute. That presents a challenge for the Android handset market as well as the PC and notebook segments, since the cost of memory will cause people to delay upgrades, hurting Qualcomm in both segments. This is not just a Qualcomm thing, this is impacting the entire industry.

For our Substack readers, I went into this in more detail when discussing Apple and explaining why I went out in May and purchased a 128GB Apple M5 Max system. Shortly after that, Apple raised prices, and that same notebook now costs an extra $2000. Analysts at the Qualcomm event raised their eyebrows at a $7000+ notebook. At the same time, it meant that Qualcomm needed to show at the event how it would attach higher-value silicon to memory and drive revenue.

From Mobile Leader to Data Center Contender

Qualcomm’s transformation starts with connectivity and custom silicon that seems like an extension of the Alphawave Semi business.

It then transitions to introducing a custom AI accelerator: the AI200, the AI250, and the AI300. The AI250 starts with HBC, which we are going to discuss after the CPU portion.

Qualcomm’s competitive position differs from Intel’s or NVIDIA’s in one critical way. The company maintains dominant positions across smartphones, PCs, automotive systems, and IoT devices while building data center capability. This breadth enables unified architecture decisions that competitors focused on single market segments cannot match.

Fiscal year 2029 revenue targets quantify the ambition:

• Total Non-Handset Revenue targets reaching $40 billion

• Data Center Revenue target exceeds $15 billion

• Automotive Revenue target is $10 billion

• IoT Revenue target exceeds $14 billion, split between $8 billion for industrial and robotics, plus $6 billion for personal AI and compute

• Non-GAAP EPS Target exceeds $18.00

The $40 billion non-handset target serves a specific purpose. Qualcomm expects to lose all Apple modem revenue by 2029 as iPhone production moves in-house. Non-handset growth must absorb that multi-billion dollar reduction while still delivering overall company expansion.

Qualcomm Dragonfly C1000 Architecture

Qualcomm is betting that its first CPU, the Qualcomm C1000, will be a big part, and the specs are certainly substantial, but there is a lot more to get into.

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I was also able to have a few neat conversations after and learned quite a bit.

Sharing the Pain and Driving Growth

Everpure has achieved significant financial and operational growth, highlighted by their first billion-dollar first quarter and an annual recurring revenue (ARR) run rate of two billion dollars.

The company says it now ships more Flash storage than anyone else and invests more heavily in research and development than all of its competitors combined, treating data storage as high technology rather than a commodity.

With an industry-leading position, Everpure expects to ship as much or more Flash this year than all of their competitors combined.

Despite this growth, Charlie openly addressed the severe pricing pressures facing the industry, noting that NAND costs have increased by six to eight hundred percent over the past six to eight months. To support their customers, Everpure made a conscious decision to absorb part of this financial burden, operating at the lowest end of their historical gross margin range to avoid raising prices too drastically.

Furthermore, the company has strictly honored all of its existing contractual commitments to make this market shift as painless as possible for its partners.

The Shift from Application-Centric IT to “Data Primacy”

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First, I wanted to recap the keynote, then go over a few of my notes from the session with Antonio Neri, who provided some context after his keynote. My reaction to the differences between HPE’s and Dell’s directions was apparently spot on.

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To many, the exact launch date is a complete mystery, seemingly chosen at random by companies as a rallying point. At Axautik Group, we have a tool to narrow launch windows. This is very important for what we do because on the STH side, we are in production with content >90 days away from publication, chips and systems arrive 30-ish days before launch, and we usually need to plan at least 2-3 quarters out to keep the pipeline healthy. We simply cannot handle “random” launch dates, so we have a methodology and a tool to handle them.

How and When CPUs are Launched

While many think there are 365 potential launch days in a year, that is not really the case. In a given year, no more than half could even be considered realistic launch days, given that a major server CPU usually has a launch event attached to it.

Projecting this to Intel Xeon 7, the first challenge is really looking at how CPUs are launched. Frankly, defining “launch” in the server CPU market is tough. Oftentimes, significant volumes are shipped to hyper-scalers before the “launch” happens. Sometimes, the “launch” event coincides with saying CPUs have shipped for revenue, even if that is an absurdly low quantity. Many in the industry do not know this, but launch timing is not directly set to product availability.

Taking an extreme example of this, Arm “launches” cores well before silicon. Illustrating this, the Arm Neoverse V3 cores were launched in February 2024. We are starting to see Graviton5 GA over two years later, and the Arm AGI CPU will use these in what is more like a very late 2026/ early 2027 era product. In traditional Intel/AMD server CPU terms, the Arm AGI CPU is probably more like a 2027 product, with general availability, and a cloud deployment can happen without the product being launched. As another example, NVIDIA will have launched Vera CPUs several times before you can buy a general-purpose server with them. Likewise, AmpereOne's “launch” is very different from when you could buy a server off the shelf with one. We are not going to use Arm vendor CPU launches because those follow a much less defined launch-to-availability-to-purchase process in a generally available server environment.

For Intel and AMD, we went back to the Sandy Bridge-EP (Intel Xeon E5-2600 V1) and Naples (AMD EPYC 7001) series launches. We also pulled in the edge compute adjacent numbers for the embedded parts, like Intel Xeon D, and mapped the launch dates. You will understand why in a future Substack. To be fair, what a launch date actually is, one could debate. For example, Intel was under pressure from SeaMicro (it is fun that Andrew Feldman now has the hot IPO’d Cerebras), so it launched the Xeon E3-1200 in a trickle in late March 2011 due to a chipset bug, but then officially launched it on April 5 of that year, skipping a quarter. Some launches are barely publicized. An example from this year is that the AMD EPYC 8005 Sorano series was “launched” during Mobile World Congress in February. There was then a GA launch, where full SKU lists were offered in May 2026. Luckily, we have been covering chip launches for a long time, so I went through and provided a bit of a filter on these to what I would consider the “launch” date on chips over the last 15 years. I am also excluding the late Opteron parts because those were effectively launched by the old AMD, and so I just wanted to look at newer parts.

With all of that, here is what the population looks like for AMD and Intel launches by year from our tool:

That is a neat view, but it does nothing to tell us when Diamond Rapids will launch. To do that, we need to delve deeper into the server CPU launch data.

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NVIDIA

NVIDIA opened the season the way it usually does, with Jensen Huang up there for the better part of two hours moving across the data center, the PC, and robotics. The piece everyone walked in expecting was RTX Spark.

NVIDIA is bringing its agentic stack to the desktop and laptop with an Arm-based Windows platform, pitched as a machine you keep at home to run agentic AI locally instead of running up a cloud bill. There were RTX Spark laptops and desktops, a DGX Station for Windows, Adobe apps getting faster on it, and a roadmap out to Vera Rubin and Rosa Feynman Spark parts later in the decade.

Indeed, there was a reason we included the NVIDIA GB10 in the recent Qualcomm Cloud AI 100 piece in this Substack.

On the data center side, Jensen confirmed that Vera Rubin is in full production and kept calling Vera a CPU built for agents rather than people, claiming 1.8 times the agentic performance of x86. He closed on robotics with Cosmos 3 and the Isaac GROOT humanoid.

Here is what I think the talk was actually about, though, and it was not the product list. Jensen was selling the idea that AI is going to every device and that it will create whole new categories of devices. The part that stuck with me, and the part I keep coming back to when I think about who wins from here, is that it is genuinely hard to justify putting money into a silicon endpoint that does not leverage AI.

AI does not just eat compute. Instead, if you consider that we are in a DRAM and NAND-constrained world, then it is harder to justify buying DRAM and NAND for non-AI-enabled endpoints. Using the logic of constraints, it is hard to replace existing infrastructure that is still operating existing pre-AI workloads. Better put, if you are going to spend on DRAM and NAND in this environment, you want it attached to an AI node, not something that will give marginal performance gains on an existing workload. The implication is that the market from PC to data center bifurcates to either higher cost AI machines or the lowest cost nodes you can get. That is a really challenging takeaway for the next few years.

Qualcomm

A quick run from the Taipei Music Hall to Nangang Hall 2, and it was time for the first keynote. Qualcomm delivered the official opening Computex 2026 keynote, with Cristiano Amon declaring 2026 the year of the agent and making the case that AI is coming to many segments at once.

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Here we have two Qualcomm Cloud AI 100 accelerators. Depending on the marketing material, these can be called the AIC100, Cloud AI100, or Cloud AI 100.

These are the smaller accelerators with 32GB of LPDDR4X memory and are connected to each other and to the host system using a Microchip PCIe switch. Also, just to be clear, these are accelerators that are not the larger, higher memory versions. This dual accelerator setup is instead something small enough that it can be packaged and placed in a notebook form factor. There was a thought that this could be an option for those who did not want to use a unified memory solution and wanted more memory than the NVIDIA RTX Pro 5000 Blackwell mobile edition at 24GB. Indeed, you can still pay a premium and order notebooks with these today.

We tried both the NVIDIA and the Qualcomm versions of this notebook, and the NVIDIA RTX Pro 5000 Blackwell Mobile edition version will have a review on the STH main site, and the Qualcomm version you will only find here for reasons that will become apparent.

Before we get too far in this, you are probably wondering whether our setup varies greatly from a reference setup. Did we see the numbers we saw because of some major setup issue? Frankly, when we saw the numbers, we were interested in this as well, so we took our results and wanted to see how close to the reference figures we were:

This type of benchmarking always has a variance, which is just part of the exercise. Still, being within 1.4% of reference numbers is close enough that most in the industry would say this is within a normal benchmark variance. In other words, our setup was performing as expected.

With that, we had a number of systems that we wanted to compare this against:

1. The NVIDIA DGX Spark (or other GB10 instances)

2. The AMD Ryzen AI Max+ 395

3. Apple Mx Max chips (M1 Max, M4 Max, M5 Max)

We decided to use the NVIDIA DGX Spark because it was the unit that is not in our 8x GB10 cluster. The AMD Ryzen AI Max+ 395 we are using the GMKtec EVO-X2 128GB. AMD has other options for that chip, but we had the GMKtec running Ubuntu, so it made it very easy to fold into our suite. For the MacBook Pro, we are using the top GPU core configuration option for each generation. The M1 Max topped out at 64GB, our M4 Max was also a 64GB configuration, and the M5 Max is 128GB. The M1 Max was relatively close in terms of release timing to the Cloud AI 100 which is why we went back to that one, plus we had the machine available.

Also, we are not doing optimization on any of these other platforms. These are just up and running, an easy path. There are so many variables doing this kind of work, so assume that for the AMD, NVIDIA, and Apple numbers, there are ways to increase performance. Also, we limited our set a bit because we needed to use models that run on Qualcomm, or that could compile somewhat easily. We are also using smaller models because we knew on the Qualcomm side that we would be a bit more limited on quantization levels, and the fact that 64GB is the least common denominator for memory capacity.

With that, let us get to the performance.

Qualcomm Cloud AI 100 Versus the Unified Memory Crowd

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Apple HAD the Best Local AI Platform, but Not Anymore

By far the best local AI platform we have in the studio is the Apple Mac Studio M3 Ultra. That may sound controversial to many, but here is why. With 512GB of memory, the system we bought a year ago for around $10,000 has been the backbone of our studio AI efforts. When we bought it a year ago, folks thought it was crazy expensive. Now, it would be silly for Apple to produce these, and that is what is happening to Apple’s entire line.

I know many folks say they have great ROI and are hammering away at agents and apps, but they rarely tell you what they are doing. We have multiple agents (mostly OpenClaw and Hermes) with Qwen3.5-397B and Qwen3.6 models running as the backend. The agents run on various compute platforms, but those Qwen3.5-3.6 models running on the Apple Mac Studio M3 Ultra 512GB have been cranking away for months. When I am in the studio, there is enough CPU and memory left over that I can use the system as a primary workstation when working in an Agentic AI builder/operator mode.

So let us get to real-world ROI.

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This morning, I read several articles on the Meta-AWS Graviton deal since I wrote STH’s yesterday. Many focused on a big win for Arm. I see it as a much more impactful deal than just that Meta is using Arm CPUs, given Arm recently launched its AGI CPU with Meta as a lead customer. Meta’s deal with AWS is much more than the AGI CPU deal with Arm, and signals a full-blown CPU land grab. In this piece, we are going to explore why.

Also, Intel’s earnings call sparked further furor over data center CPU excitement. Although in Taiwan earlier this month, it was clear that Intel has some headwinds as well, which we may save for the next post.

In our STH Labs, we have been profiling dozens of agentic AI workflows and CPUs against them, and we will be sharing those results soon. Anyone saying Meta is doing this solely because of a focus on Arm would be foolish. There is a lot more going on here.

Let us get into it.

The Checkers Versus Chess of the Meta and AWS Announcement

Mainstream media reported that it was a big win for Arm that Meta was using its Graviton chips. That is a simple observation, and a fair one. Meta using more Arm will be good for the Arm ecosystem, even though hyper-scale CPU use is only sufficient up to a point, because their software stacks end up being more homogeneous than the broader market. Meta did not just buy CPUs, and that is what makes this interesting.

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Introduction: The Case for HBM3E PCIe GPUs with High Bandwidth and Capacity

The AI revolution has created an unprecedented demand for compute resources that can handle increasingly large models. While much attention has focused on data center accelerators connected via NVLink, InfiniBand, Ethernet, UltraEthernet, and so forth, there exists a significant opportunity in the traditional PCIe GPU market that remains largely unaddressed by today’s accelerators. The industry needs an HBM3E-based PCIe graphics card that delivers both high bandwidth and high memory capacity in a form factor compatible with existing server infrastructure.

Current AI workloads face a fundamental bottleneck: the trade-off between model size and available memory. The answer, if you want to run big models fast, is to buy a rack-scale GPU cluster, get a lot of power to run it, and have at it. While that is great, not everyone has a multi-million dollar budget to implement that plan, and just finding power is not easy anymore. So let us start small and work up.

At STH, we have ten NVIDIA GB10 systems and have an 8-node GB10 cluster with 200GbE RDMA networking running. It runs large models like Kimi-K2.5 but slowly because each node has limited memory bandwidth and only 128GB of capacity. Likewise, the AMD Ryzen AI Max+ 395 systems at 128GB run into memory bandwidth and capacity challenges. Our Apple Mac Studio M3 Ultra 512GB has better memory capacity and bandwidth, but we may need 1-3 more because we have seen it drop to single-digit tokens per second while processing 150K+ context tokens. It is super fast, until it goes so slowly that you can clock it with a sundial.

All of these are instructive for the need for a data center PCIe GPU because they address memory capacity, enabling large models at the expense of speed. The main alternatives to these would be getting an NVIDIA RTX Pro 6000 Blackwell with 96GB of GDDR7. That has more FLOPS and higher memory bandwidth, but a GB10 can run larger models and retain more context due to its capacity.

The NVIDIA GB300 Station deserves special mention, as it features a de-rated 252GB of HBM3E memory from the higher-end Blackwell Ultra servers. In a 1.6kW power budget for the entire system, you only get one of these GPUs in the GB300 Station platforms. That means a cluster of four GB10’s will be vastly slower, but will run larger models. As a result, NVIDIA has a Grace CPU with 496GB of memory to help expand the total memory in a system. People want more, so now you can also add a 96GB RTX Pro 6000 Blackwell.

When we look at what you can put into servers, a standard PCIe GPU that fits into a standard CEM slot, it feels like the world has forgotten this segment. Four GPUs, eight GPUs, or even just one or two in a standard server. This is a form factor and segment that are somewhat compatible with existing infrastructure and with which people are familiar.

We did a guide on this in 2025, called The 2025 PCIe GPU in Server Guide, and it was extremely popular, garnering over 170K views each on both the written and video forms. This has been a popular topic folks have been researching for the last nine months. At the same time, there is no true PCIe GPU flagship for this generation that combines leading memory capacity, ample memory bandwidth, and a lot of FLOPS. That is a challenge.

Benefits of High-Bandwidth, High-Capacity GPUs for AI Models

Memory bandwidth and capacity directly determine what AI models can run efficiently on a given system. HBM3E technology offers substantial advantages over traditional GDDR memory architectures. The three-dimensional stacking approach enables significantly wider memory interfaces within the same physical footprint.

For AI inference workloads, memory capacity and memory bandwidth often matter more than raw FLOPS. A model must fit entirely within GPU memory to avoid costly swaps to system RAM or storage. We are already running models in the lab that require 800GB or more of memory between the model and its context storage, and we are on the verge of a new generation of larger models that could be quantized down to that range but will use a lot more memory. That 800GB figure is important because 96GB per GPU and 8 GPUs is 768GB of memory. Unfortunately, memory capacity is one where you either have it or you do not, but you are always trying to get right up to the limit.

High bandwidth of that memory ensures that once a model is loaded, data can flow to compute units without creating bottlenecks. Transformer architectures particularly benefit from sustained memory throughput during attention operations and token generation phases. The combination of high capacity and high bandwidth enables organizations to run larger models at higher batch sizes while maintaining acceptable latency profiles. Our NVIDIA GB10 cluster has the capacity, but with LPDDR5X and then having to sync over the network in a TP=8 configuration, it is like an extreme case of “it works” but it is slow. Just like when we ran a large BF16 Deepseek-R1 model on an AMD EPYC server.

When you have tested and used the extreme memory bandwidth starved configurations to get capacity, you crave speed. On the other hand, when you have traded capacity to get that speed and lose the accuracy of the models you are running, you quickly yearn for capacity.

If you are searching for a GPU server that uses “only” 5kW for four GPUs or 10kW for and eight GPU system, your chance with a more advanced solution like the HGX NVL8 platforms stopped somewhere around NVIDIA Hopper. PCIe GPUs at around 600W each (some can do more with liquid cooling) mean you can build servers to hit those rack power limits and retrofit them into existing data centers.

That begs the question, what is out there? Let us get to that next.

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On the STH main site, I did a quick write-up of the event and the new chips. We will, of course, have more on them later this year as they seem to be a later product in 2026, being announced in Q1 2026. I also got asked for perspective from a number of folks, so I wanted to share a bit of a different perspective.

Perhaps the big question of the day was how Arm is competing with its customers. For that one, I have a very different take than I probably would have had if the chip had been announced five years ago. Let us get to that next.

Arm Competing with Customers with the Arm AGI CPU? Yes… but…

If you ask about the key drivers for Arm CPU growth, there are really two. First, hyperscalers. Second, AI. The fact is that AMD EPYC did so well scaling cores and using the latest TSMC nodes that it is largely carrying the x86 market at this point. To be clear, Arm counts both Intel and AMD as customers, and surely a new CPU is a competitor. Still, there are several Arm CPU vendors in the market now that probably care more about Arm making its own CPUs. Let us go through a few of those and discuss the competitive landscape.

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1. Large-scale AI Factory compute - These are the well-known AI providers and clusters. Also, large-scale computing facilities can operate in a similar tier for some industries (e.g., in drug discovery)

2. Local or Employee Scale Agentic AI - This, I will argue, encompasses everything from what sits at a person’s desk or cubicle, up to small clusters

3. On-device AI - This is the domain of physical AI that often has hard constraints to achieve a mission with limited connectivity and power envelopes

The first tier of the frontier model, hosting and high-end AI factories, makes sense. In large-scale systems, the cost of delivering used and useful tokens can be driven down at an exceptional rate. The cost lever of scaling out these AI factories with new infrastructure generations, folks are hyper-focused on. What perhaps garners insufficient attention is the successful completion of tasks and the compute and tokens required to achieve them. If you have ever seen a task fail after a million or several million tokens burned, you will know the exact challenge. Higher success rates mean workloads transition more quickly.

Large-scale AI factories are absolutely necessary. The simple reason is this: agentic workflows need to scale out, and at speed. When agents are talking to agents, the accuracy and speed metrics will dominate. Years ago, I worked on a project for a larger enterprise IT company where the primary goal was simply to beat a larger competitor’s time to do the quote-to-order process because it found that it was losing a large number of deals (double-digit percentage of revenue) simply due to being slower than its competitor. Partners and customers would frequently pick the other vendor just because they were faster. The same will happen with agent-to-agent communication.

On-device AI has its own constraints. If you do not have strong connectivity and are operating on battery power, that naturally limits how much compute you can have, which makes this its own mega-tier.

Still, at some point, individuals and organizations will gravitate toward a mix of both, using AI factories and some sort of local or employee-scale AI infrastructure. Controlling costs and ensuring that data traversals are well-understood are reasons for this, but there is a more practical one: it fits into the existing employment paradigm.

First, we will quickly recap the common platforms for this local or employee-scale AI. Then, I want to make a case for how these platforms fit.

What Would You Buy Today for Local or Employee Scale Agentic AI?

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NVIDIA’s Quantum-X Photonics

The first co-packaged optics switch NVIDIA has widely shown, and has been showing for some time, is the NVIDIA Quantum-X InfiniBand Photonics Switch.

NVIDIA has already stated that this is an early implementation of its co-packaged optics. Perhaps the interesting part is that you can see 18 pluggable light sources and 144 MPO/MTP fiber ports. That is still a lot of 800Gbps ports, but the box is huge.

NVIDIA Spectrum-X Pluggable Optics Liquid-Cooled Switch

Taking a quick detour for a moment is the NVIDIA Spectrum-X Ethernet switch using pluggable optics.

This design packs 64 ports into 2U of rack space. You can see liquid cooling and internal cables to connect the ports.

This is an interesting design since the cooling for the optics is the majority of the 2U faceplate, along with the internal chips. Even just between this, with 64-ports in 2U versus the Quantum-X CPO with ~36 ports per U, you can see where NVIDIA is going.

NVIDIA Spectrum-X Photonics

When we say that the NVIDIA Quantum-X is more of a first-generation product and Spectrum-X is a refinement, you can see it clearly in the packaging. Spectrum-X increased the integration, but also has a neat form factor.

NVIDIA also had its 2U co-packaged optics switch on display at CES 2026, and the fact that it is a 2U switch is the most unremarkable part of it.

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As soon as the earnings presentation came out, this slide was nothing short of baffling.

First off, I am not sure that this is a story of growth when you look at the revenue for companies like AMD and NVIDIA. Indeed, NVIDIA’s networking business that stems from NVIDIA buying Mellanox out from Intel in 2019 is on track to look like a better business alone than Intel Products will in 2026. If you want a story on how that deal went down, here is an older post for you.

My biggest challenge with Intel’s FY2025 revenue slide was simply “AI driving growth across our businesses”. I am not entirely sure that, in the context of AI buildouts, where $13.7B in systems for a single data center buildout would not even raise an eyebrow. Let me put this into a clearer context for you.

Just after NVIDIA GTC 2025, we filmed the Factory that Builds AI Factories video. That was in the era of NVIDIA GB200 NVL72 racks, whereas I would be certain that both Dell and Supermicro are more focused on GB300 NVL72 now, versus three quarters ago.

When we did that video, a GB200 NVL72 rack was generally considered a $2.75-3M rack. Memory pricing, higher-end networking, and systems updates have changed a NVL72 rack pricing over the last year, but that $13.7B of quarterly Intel revenue if we are talking “AI demand” is roughly 5000 of NVIDIA’s GB200 NVL72 racks using Q1 2025 pricing.

That is 360,000 NVIDIA B200 GPUs and 180,000 NVIDIA Grace CPUs plus all of the networking and other bits that go into these racks, but it does not include additional racks of networking, storage, and support servers that sit around these in a cluster.

Even with Intel’s client business still at a higher revenue figure than its data center business, Intel’s revenue, as a whole, is like one large AI data center’s worth of just the AI racks per quarter.

Since I have already been on manufacturing floors for GB300 NVL72 racks this quarter, seeing “AI driving growth across our businesses” might be a forward-looking statement, but I could not align what I have been seeing and experiencing with the statement and historical revenue figures.

Then Came the Clear Clearwater Cloaking

Many folks have discussed the “Demand outpacing supply across server and client” and having competing core tiles for client and server. One needs to remember that even within server, Intel has competing 18A core tiles.

Clearwater Forest and Diamond Rapids will need to use different 18A tiles. Diamond Rapids is what would be used in a modern AI server. Clearwater Forest is aimed at cloud-native workloads. As a quick recap, Clearwater Forest and Diamond Rapids were Intel’s main server products launching in 2026. Clearwater is the E-core or efficient core part that was built at a time when Intel was focused on delivering an answer to lower-end Arm Neoverse cores being adopted by hyper-scalers. The theory was that de-featuring x86 cores removing features like Hyper-Threading, big caches and AVX pipelines, and so forth would reduce the footprint of server CPU cores so more could fit on a package. In addition to that, removing Hyper-Threading helps Intel from a security standpoint after having dealt with Spectre/ Meltdown and having to rush a Cascade Lake fix generation in 2019.

Just a few months ago Clearwater Forest-AP, the company’s 18A server part that brought more advanced packaging to the data center, was touted as a major leap over Sierra Forest-SP/-AP. After the company’s event in October 2025, the question I posed to Kevork Kechichian, GM of DCAI at Intel, was around the part’s proposed value proposition. While it uses Intel 18A, the manufacturing complexity appears to increase significantly, while the performance gains shown were modest.

Per core performance is not a trivial metric. It was one of the major challenges Ampere ran into with its AmpereOne (and Altra/ Altra Max) lines of Arm CPUs. In x86 AI servers, generally we see either very high core count CPUs, or we see higher-frequency 64-core CPUs. When an entire system can be blocked waiting for a single thread, having more low-performance cores does not matter. Instead, you can think of the E-core strategy is basically making many low-performance cores for web hosting, low performance virtualization, and there are also pockets of telecommunications that work very well with E-core designs. Sure there are other areas, but conceptually, think of an E-core CPU’s value as having stable low-to-mid performance. AI servers, in contrast, are focused on removing tail latencies so that huge numbers of silicon components can all run at top performance.

Then came Intel’s earnings call where the bombshell was in the omission.

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The Common Theme with New AMD Ryzen AI Max+ 395 Systems

As a quick reminder, the AMD Ryzen AI Max+ 395 “Strix Halo” parts are fascinating. They have both high-performance Zen 5 CPU cores, along with large integrated GPUs. The top-end model can also be equipped with 128GB of LPDDR5X memory, and 96GB of that 128GB can be dedicated to the large onboard GPU. As a result, these parts have become the go-to AI development parts, whether they are in notebooks or in desktops. For the past several months, the lab has had four of these systems running as part of our edge AI cluster, comprised of these AMD systems, NVIDIA GB10 + GPU systems, and Apple Mac Studios. Hands down, right now, if you want a compact AMD AI box, the Strix Halo is the hot item.

That brings us to CES 2026 and our discussions with companies on plans to expand their lineups with the parts.

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Here is the video if you have not seen it yet.

In the Equinix SV11 portion of that video, we went into the NVIDIA DGX SuperPOD. This is a cluster of eight NVIDIA GB200 NVL72 racks along with the associated networking, storage, and cooling. The significance of the installation in SV11 is twofold. First, it was an opportunity to put a DGX SuperPOD in Equinix in Silicon Valley so that other customers and partners could access it. This SuperPOD is designed to sit outside of the NVIDIA firewall. That is why this SuperPOD is often used for GTC stage demos. The second significant impact of this installation is that NVIDIA is using it as a template to bring out to Equinix (and other) colocation sites around the world.

In that second point that Charlie and I talked a bit about, and he had some really interesting insights. At some tech companies, VPs have limited knowledge of their products. Charlie is perhaps the exact opposite as sometimes when I chat with Charlie I wonder if he knows the torque values of every screw. Still, his perspective is vastly different than many AI startups discussing their systems.

10,000 Precision Welds in Your AI Clusters

That brings us to this photo from when Charlie and I were inside the roughly 1MW NVIDIA DGX SuperPOD.

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This is Meta’s Massive Plan to Recycle DDR4 Memory and Save Huge

Not many of the hyper-scale customers are talking about their plans to add disaggregated shared memory, but we know Microsoft and others are also working on CXL solutions. Sometimes, shared memory just shows up casually in presentations like at Hot Chips in 2024, where Meta was showing its MTIA AI accelerator architecture and casually has a “Memory Expansion” feature that was on the slide but not covered in the presentation.

Recently, we did a piece on the STH main site around the Marvell Structera CXL Expansion devices.

As part of that, we showed how hyper-scalers can reuse their DDR4 memory by recapturing it from their retiring servers. Putting it into the Structera X CXL expansion devices, allows companies to not just add the physical DRAM capacity, but to also add encryption and compression to the memory. With a 1.8-2.0x compression ratio, a recycled 128GB DDR4 DIMM becomes up to 256GB of effective memory capacity. That is the miracle of recycling DDR4 DRAM from retiring servers. Not only is it “free” to get the DIMMs, but you get more memory capacity than you salvage.

What we showed does not look like it is for Meta, or at least for Meta’s ultra-high volume platforms. Instead, it is for another hyper-scale customer, doing something similar. There is a giveaway that this is not the Meta board.

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Intel’s Confirmation on the Diamond Rapids Roadmap Change

We had multiple sources, enough to publish on, so I sent a note to Intel last night, and they quickly sent the following statement:

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