This week gave a good reason to take stock of what that change actually looks like.

What happened at SEMICON Taiwan

On September 2, Google’s SVP and chief technologist for AI infrastructure, Amin Vahdat, gave the opening keynote at SEMICON Taiwan, his first public address in Asia. The headline: Google’s TPU releases, which used to arrive roughly every two years, are now shipping annually, and the company is pushing toward two releases a year, with more planned after that.

Vahdat also confirmed Google is growing its Taiwan R&D footprint by 60%, expanding office space in Taipei’s Shilin district. He called Taiwan Google’s largest hardware engineering base outside the US, one where Google engineers work directly with local manufacturing partners on everything from chip bring up to advanced packaging, liquid cooling, and high power system design.

None of this is a chip launch. It’s a progress report on a strategy that’s been building for most of 2026, so it’s worth walking through the pieces in order.

The cadence, in one picture

Google’s own generational history makes the acceleration easy to see. Early TPUs shipped on a multi year cycle. Recent ones have compressed to about a year apart, and the eighth generation broke from a single chip per generation entirely, splitting into two purpose built parts released together.

Google TPU release cadence: the gap between generations has shrunk from three years to about one.

What actually shipped: TPU 8t and TPU 8i

The generation that set this cadence shift in motion, TPU 8t and TPU 8i, was unveiled back in April at Google Cloud Next, not this week. It was the first time Google split a single TPU generation into two chips built for different jobs instead of one general purpose part asked to do everything.

The design logic is straightforward once you see it laid out. Training wants the biggest possible shared memory pool so a model can spread across as many chips as possible without stalling on data movement. Inference, especially for AI agents that plan, call tools, and juggle multi step tasks, cares more about latency and about not wasting compute cycles on the housekeeping work of keeping chips in sync. Splitting the chip in two lets Google optimize each side without compromise.

The supplier map has gotten a lot more crowded

Google used to lean almost entirely on Broadcom to help design its TPUs. That’s no longer the picture.

Broadcom’s relationship is now locked in through 2031 for TPU design and supply, according to SEC filings. MediaTek has become a genuine second design partner, reportedly earning a bigger role than expected on the eighth generation TPU line; Taiwan supply chain reporting actually points to a role reversal from what most people assumed, with MediaTek involved in the training focused TPU 8t and Broadcom on the larger inference focused TPU 8i. Google hasn’t confirmed that split publicly, so treat it as well sourced reporting rather than an official statement.

Marvell is the newest addition, and it isn’t trying to out compete Broadcom or MediaTek for a TPU generation. Its July 2026 agreement with Google covers the silicon that attaches to the TPU stack: inference accelerators, storage controllers, network interface controllers, memory interface controllers, and near memory compute. Think of it as Google building out the rest of the rack around the TPU core rather than replacing anyone.

How Google plans to scale this into a real business

Three moves explain how an internal chip program becomes an external product line.

Selling hardware directly, not just cloud access. Until this year, the only way to use a TPU was to rent one through Google Cloud. In April, Alphabet said it would start selling TPU systems for installation in customers’ own data centers, aiming first at AI labs, capital markets firms, and high performance computing users. By July, Google confirmed the first real deliveries had gone out and the first hardware revenue had been recognized, with most of that revenue expected to land in 2027. Those hardware contracts now sit inside Google Cloud’s backlog, which reached $514 billion in the most recent quarter.

Diversifying who builds the chips. Spreading design work across Broadcom, MediaTek, and Marvell reduces Google’s dependence on any single partner and, not coincidentally, gives Google more leverage in pricing and capacity negotiations. It also means Google can specialize differently across the stack instead of asking one partner to be good at everything.

Backing up the manufacturing. Google has reportedly lined up Intel as a secondary foundry for chips due around 2028, on top of its primary reliance on TSMC. Combined with the Taiwan R&D expansion, this points to a company trying to make sure supply capacity doesn’t become the bottleneck once demand for external TPU sales actually shows up.

Where the growth estimates come from

The revenue and shipment numbers floating around aren’t Google guidance. They’re analyst models built on top of what Google has disclosed about capacity, pricing, and backlog.

GF Securities models shipments rising from 2.76 million units in 2024 to 8.8 million by 2027. Morgan Stanley, using a different lens, has revised its TPU related Google Cloud revenue estimate up to $84 billion in 2027 and $108 billion in 2028, after Google’s pricing per gigawatt of deployed TPU capacity came in higher than the bank had assumed. Both estimates could be wrong in either direction. Execution risk is real: converting backlog into recognized revenue takes time, and scaling three separate manufacturing partners at once is a harder operational problem than scaling one.

The takeaway

Two chip releases a year instead of one every other year. A supplier base that’s tripled in the space of a year. Hardware now shipping to customers who install it themselves. A Taiwan engineering team growing 60%. None of these facts alone would be a big story. Together, they describe a company converting an internal tool built to keep Search fast into something that increasingly looks, and increasingly gets valued, like a chip business in its own right.

NBO: It starts as a hunch, and a lot of it is noise

Every opportunity pipeline begins at the widest point: the New Business Opportunity, or NBO. Somewhere in the field, a regional sales manager or a distributor partner believes there might be a shot at winning a piece of business. Doesn’t matter how thin the odds are. They log it into the sales management system, and it becomes an entry in the pipeline.

This is the noisiest stage by far, and I mean that literally. A meaningful chunk of NBOs are junk. Some get double counted, the same underlying opportunity entered twice by two different people who never compared notes. A distributor sometimes logs a placeholder entry for a deal that might materialize someday, just to have something in the system. A sales rep hears secondhand that a friend of a friend at some company might need a part, and that becomes an entry too, with nobody checking whether the conversation ever actually happened. And because entries are typed in by hand, fat-finger errors are common: someone adds a zero to a genuine $10 million opportunity and it shows up in the system as $100 million. Nobody catches it because nobody is auditing NBOs closely, that’s not what this stage is for.

A company with a large, active sales network will always show a large NBO count, because logging a lead costs almost nothing and the incentive is to capture everything that might eventually matter. None of that makes the aggregate number meaningless, but it means the raw NBO total should be treated as closer to a lead list than a forecast.

SBO: Someone has to check if it’s real

The next stage filters that noise. It’s usually marketing that reviews the NBO and asks the basic questions: does the cost structure work, does this fit the target market, is this customer and this opportunity actually real. If it survives that review, it graduates to a Supported Business Opportunity, or SBO.

This is the first real qualification gate. An SBO means the company has decided the opportunity is worth tracking seriously, not that it’s been fully vetted for revenue.

Design In: a real signal, but not a done deal

Once an opportunity is supported, customer engagement deepens. Technical routines start running between the two sides. At some point, the relationship crosses into what’s called a Design In.

Design In isn’t a vibes-based judgment call. It’s usually anchored to concrete criteria: a written commitment from the customer, along with design schematics showing the part is actually specified into their system. That’s what separates it from the earlier stages, which can be driven by not much more than a sales rep’s optimism.

But even a Design In doesn’t guarantee revenue. Customers frequently design in two suppliers for the same socket, deliberately. Sometimes it’s to see which one delivers the better technical solution before committing. Sometimes it’s a conscious multi-sourcing strategy so they’re never dependent on a single supplier. Either way, two companies can both legitimately claim the same Design In, and only one of them (or neither, if the whole program stalls) ends up shipping. So Design In is a genuine signal of engagement, but on its own it’s still not a reliable predictor of revenue.

Design Win: the order lands, getting closer to revenue

From Design In, the technical collaboration continues and the customer starts driving toward production. When the customer reaches mass production readiness and issues the first purchase order, that’s a Design Win.

It’s worth being precise about what a Design Win actually is: it’s Mass a customer commitment, a PO. It is not revenue. Revenue only gets booked once the supplier actually ships the product against that PO. A Design Win with no shipment behind it yet is still, technically, zero dollars on the income statement.

Mass production: this is where revenue starts

Once shipments against the PO begin, that’s the mass production phase, and this is the point where the pipeline finally turns into actual revenue on the income statement.

Conversion ratios: this is where the real story is

Everyone wants to know what percentage of a pipeline actually turns into revenue. The honest answer is: it depends enormously on who’s building the pipeline.

For a well-established business with a proven track record, a mature customer base, and a track record of shipping in volume, I’ve seen Design In to revenue conversion ratios around 15%. That’s a business customers already trust. They’ve qualified it before. There’s a reasonable base rate that a design in becomes a design win becomes shipped product.

Compare that to a startup. I was once involved in acquiring one, and its Design In to revenue conversion ratio was almost zero. We didn’t buy it for its pipeline. We bought it for its IP. The pipeline was close to worthless because large customers generally don’t want to build their systems around a startup’s silicon. The question they’re implicitly asking isn’t just “does this part work,” it’s “what’s the guarantee this company will still exist in six months?” An automotive or hyperscaler customer qualifying a part is signing up for a multi-year relationship, spare parts, support, and roadmap continuity. A startup can’t credibly promise any of that, so even a technically strong Design In tends to stall rather than convert.

This is the single biggest reason a raw pipeline number is close to meaningless without context: a $1 billion pipeline from a 20-year-old supplier with a 15% conversion rate is worth roughly $150 million in eventual revenue potential. The same $1 billion pipeline from an unproven company with a near-zero conversion rate is worth closer to nothing, no matter how good the underlying technology is.

Why the headline Design Win number is usually bigger than what actually ships

One more piece people get wrong: a Design Win is not a single check that clears, and the dollar figure attached to it isn’t fully reliable either.

Two things inflate it. First, a Design Win of, say, $50 million is typically the total value over the life of that design being shipped into a customer’s product, not $50 million landing in a single year. Second, the size of that number itself tends to run hot. Customers are ambitious about how much of their own product they expect to sell, and they forecast the opportunity accordingly. On the supplier side, sales bonuses are often tied to the size of the Design Win booked, which creates a real incentive to justify a higher number rather than a conservative one. Put those two together and it’s common for actual shipped revenue to land meaningfully below the originally announced Design Win size, in my experience often around 80% of it.

So the fuller version of the math is:

Annual revenue contribution ≈ (Design Win value × ~80% realization) ÷ opportunity lifetime

If a Design Win is announced at $50 million, realistic shipped value is closer to $40 million, and if the part ships for 5 years once it’s in production, that’s roughly $8 million a year, not $50 million in year one and not even $10 million a year. Automotive and industrial design wins in particular can have lifetimes of 7-10 years once a part is designed into a platform, which stretches the annual contribution even further. This is why headline Design Win values in press releases can be dramatically bigger than what shows up on the following year’s income statement, and it’s not necessarily bad faith, it’s just how the incentives and the math work.

So what does $1.2B pipeline actually tell you?

A pipeline figure like Sivers’ is almost certainly an aggregate across some combination of these stages, not committed revenue and not a forecast. It represents the total addressable value of opportunities currently being tracked, weighted by nothing in particular unless the company says otherwise. Without knowing the stage mix (how much is noisy NBO versus Design In-or-later signal), the applicable conversion rate, and the typical cycle time, the number is directional at best.

My assessment of Sivers: does the pipeline number deserve trust?

This is where I want to be direct rather than diplomatic, because a pipeline is only as credible as the management team reporting it. I went back through Sivers’ last several quarters of disclosures to check.

Revenue has actually been declining while the pipeline narrative has been accelerating. Q1 2026 revenue came in at SEK 61.9 million, down 22% year-over-year (photonics alone fell 32%). Q2 2026 revenue was SEK 53.8 million, down 12% year-over-year from SEK 61.4 million. H1 2026 revenue overall fell 20% year-over-year to SEK 115.6 million. Over that same window, the pipeline went from $453 million at year-end 2025, to $799 million in Q1 2026 (+77% YTD), to $1.2 billion by July 2026 (+268% since year-end 2025). Sivers’ own investor communications have acknowledged the gap directly, framing it as “one number shows what we delivered, the other shows the opportunity ahead.” Said once, that’s a fair thing to say. Said across consecutive quarters of declining revenue, it starts to look like the pipeline figure is doing the job of holding investor attention while the reported numbers soften.

Guidance has been pushed to the right. At its May 2025 Capital Markets Day, management guided to 3-4x revenue growth over 4-5 years and reiterated 20-30% aggregate annual growth in the Q3 2025 call. Full-year 2025 revenue did grow 25% (33% in constant FX), broadly consistent with that guidance. But through H1 2026 the story has shifted: management now points to a “revenue inflection in Q4 2026” and calls 2027 the “transformational year,” with no formal financial forecast published for the current period. Moving the growth story further out while simultaneously touting record pipeline growth is a pattern worth watching closely over the next two quarters.

The financial restatement is the bigger red flag. In connection with evaluating a Nasdaq New York dual listing, Sivers had to align its 2024 and 2025 financials with PCAOB audit standards. The result: the 2024 net loss was revised from SEK 116.3 million to SEK 183.9 million, a 58% increase in the reported loss. The 2025 net loss was revised from SEK 186.5 million to SEK 222.6 million, a 19% increase. Full-year 2025 EBIT was reset to SEK -177.8 million and adjusted EBITDA to SEK -50.3 million. Equity dropped from SEK 1.08 billion to SEK 949.8 million. The annual report was delayed twice in the process (first from April 27 to May 15, then the Q1 2026 report itself slipped from May 20 to May 29). None of this is illegal, and restatements do happen when a smaller company scrambles to meet US audit standards for the first time. But it means the historical financials investors were pricing the stock against for over a year materially understated the losses. That’s exactly the kind of thing that should make you discount management’s forward-looking statements, pipeline figures included, until they’ve rebuilt a track record of clean reporting.

Bottom line:

I will not take the $1.2 billion pipeline number as a reliable predictor of revenue on its own. The stage composition hasn’t been disclosed. The conversion rate hasn’t been disclosed. Revenue has declined for two consecutive quarters even as the pipeline figure has been the headline of every release. And the restatement means the pre-2026 baseline itself needed correcting upward on losses. A pipeline is a genuinely useful operational metric when a management team has earned the credibility to report it plainly. Right now, I’d want to see the promised Q4 2026 inflection actually show up in reported revenue, not just referenced in guidance, before treating Sivers’ pipeline growth as a leading indicator rather than a narrative choice.

There are two competing methods for joining those layers: conventional bump-based bonding (like SK Hynix’s MR-MUF) and hybrid bonding.

What Do SK Hynix and Samsung Do?

SK Hynix uses MR-MUF (Mass Reflow, Molded Underfill), its own mature, proprietary process. Tiny solder bumps on each die are melted together across the whole surface at once (”mass reflow”), then a liquid epoxy is injected into the remaining gaps and hardened (”molded underfill”) to reinforce every joint mechanically. SK Hynix has refined this process for years and plans to keep using it as the primary method through HBM4 and HBM4E.

Samsung, historically, has used a different conventional method, thermo-compression (TC) bonding, rather than MR-MUF. But Samsung is now planning to partially adopt hybrid bonding starting with 16-high HBM4E, branded as “hybrid copper bonding” (HCB). Samsung has publicly shown HCB samples and says it can cut thermal resistance by more than 20% versus TC bonding. This is a partial, selective introduction, not a wholesale replacement of TC bonding, and full-scale, high-yield mass production is still targeted for around 2029 to 2030, similar to SK Hynix’s timeline for full adoption at HBM5.

Why Is Hybrid Bonding the Future?

Hybrid bonding skips solder entirely. Copper pads on two dies are pressed together at room temperature and then fused directly through heat treatment: copper to copper, with the surrounding oxide layers bonding to each other too. No bumps, no underfill, no gap.

The payoff: bonding pitch (spacing between connections) shrinks to under 18 micrometers, versus roughly 30 micrometers for solder bumps, enabling much denser interconnects. Removing the bump and underfill layer frees up vertical space, letting core dies run thicker at the same total stack height. And a solid, continuous copper and oxide interface conducts heat much better than solder and epoxy. Thermal resistance drops meaningfully, which matters as stacks get taller and hotter. It’s the only realistic path to 20-layer-plus HBM stacks.

Hybrid Bonding Isn’t New

This isn’t unproven, exotic technology. Hybrid bonding has been used in CMOS image sensors since around 2010, where Sony pioneered wafer-to-wafer bonding to stack a sensor’s light-capturing layer directly onto its logic layer. It’s also already in mass production in memory: YMTC, China’s largest NAND maker, has been mass-producing 3D NAND using wafer-to-wafer hybrid bonding under its “Xtacking” brand since around 2018 to 2019, roughly seven years of real production experience. YMTC built such a strong patent position in hybrid bonding that Samsung itself had to license YMTC’s technology to build its own next-generation, 400-plus layer NAND. So the basic physics is thoroughly de-risked elsewhere in the industry; the hard part is scaling it to HBM’s specific demands.

HBM Will Expand the Market, But SK Hynix Just Delayed Adoption

Hybrid bonding’s track record in image sensors and NAND, combined with HBM’s explosive volume growth, is exactly why analysts expect HBM to be the technology that pulls hybrid bonding into true mass market scale for logic-adjacent memory, a much bigger stage than image sensors or NAND ever offered it.

But at Hot Chips 2026, SK Hynix’s VP of Package Engineering, Jaesik Lee, confirmed hybrid bonding won’t be used for the upcoming HBM4E generation. Full adoption is being pushed to HBM5, with full-scale production not expected until roughly 2029 to 2030.

Why the Delay? (In Detail)

This deserves unpacking, because it isn’t one simple reason. It’s several forces stacking on top of each other.

1. Yield math gets brutal at many layers. Bonding two dies together with hybrid bonding works well; it’s been proven for over a decade in image sensors, which typically only need one bonding interface (sensor layer to logic layer). HBM is a completely different challenge: you need 16, and eventually 20 or more, successful bonding steps in sequence, one per layer. Even a small failure rate at each individual step compounds fast. If each bond has, say, a 99% success rate, which sounds excellent on its own, stacking 16 of them in a row means the overall stack succeeds only about 85% of the time. Push to 20 layers and it drops further. Manufacturers need each individual bonding step to be almost perfect, not just good, for the economics to work at the volumes AI chip customers demand. That level of precision, repeated reliably across many layers, is what SK Hynix’s Jaesik Lee called “really challenging.”

2. Alignment errors add up layer over layer. Each bonding step requires aligning two dies with sub-micron precision. Do that once, and it’s very achievable. Do it sixteen times in a row, with each new layer needing to align precisely not just to the layer below it but to the whole stack’s cumulative position, and small misalignments can build on each other, similar to stacking sixteen pieces of paper by hand and expecting every edge to still line up perfectly at the top.

3. Surface cleanliness requirements are extreme. Because there’s no solder to “absorb” small imperfections the way a melting solder ball can compensate for slight unevenness, hybrid bonding surfaces need to be essentially free of any particle, scratch, or contamination across the entire bonding area. A single microscopic speck of dust can prevent proper bonding across a much wider area than the speck itself, and keeping that level of cleanliness consistent across every one of sixteen-plus bonding steps, at high volume, in a live factory, is a very different challenge than achieving it once in a lab demonstration.

4. A standards change reduced the urgency. JEDEC, the body that sets official memory specifications, raised the HBM4 package height ceiling from 720 to 775 micrometers, deliberately matched to the standard thickness of a logic wafer, since the HBM stack sits right next to the GPU die and both need to end up at the same height after the whole package is ground flat for cooling. That extra headroom let SK Hynix and Samsung keep scaling capacity (going from 12-Hi to 16-Hi stacks) by simply making each individual die thinner, rather than being forced into a new bonding method sooner. Industry discussion is already underway about relaxing the ceiling even further, to somewhere between 825 and 1,000 micrometers, for future 20-Hi HBM5 stacks. If that happens, it buys the current bump-based methods even more time, because the core motivation for hybrid bonding (fitting more layers into a fixed, tight height) becomes less urgent when the height limit itself gets more generous.

5. Customer demand for very tall stacks arrived slower than expected. Reports indicate that demand from major GPU customers, including Nvidia, for 16-high HBM has been more limited than anticipated, with 12-high HBM4E still expected to remain the mainstream product for now. Without urgent customer pull for the tallest stacks, there’s less commercial pressure to rush an immature bonding process into production.

6. Alternative thermal fixes bought more breathing room. Both Samsung and SK Hynix have been developing their own proprietary heat dissipation improvements (like SK Hynix’s i-HBM) that improve thermal performance without requiring a full switch to hybrid bonding. This gave both companies a way to address part of the thermal problem hybrid bonding was meant to solve, without needing hybrid bonding itself to be ready yet.

Put together: hybrid bonding isn’t being delayed because the idea failed. It’s being delayed because doing it reliably across many memory layers, at commercial yield, is a harder engineering problem than doing it once or twice (as image sensors and NAND do), and because a standards relaxation plus slower-than-expected demand for the very tallest stacks removed some of the time pressure to solve that harder problem right now.

Implications

For GPU makers and hyperscalers, this means the current bump-bonding-based supply chain has more runway than expected, reducing near-term technology risk through the HBM4/HBM4E era. For SK Hynix, it’s a deliberate bet against rushing an immature process into mass production and risking yield collapse at scale. For Samsung, its willingness to partially introduce hybrid bonding earlier, at 16-high HBM4E, becomes a real competitive variable: if its yields mature faster than expected, it could gain ground in the run-up to HBM5. And HBM5 itself is shaping up as a bigger architectural leap than usual, bundling full hybrid bonding adoption with new thermal engineering rather than spreading changes across generations.

Equipment Makers Impacted

The delay directly affects the timing of capital equipment demand. The hybrid bonding tool market is concentrated among a handful of specialists. EV Group (EVG) and Besi are the two leaders: EVG dominant in wafer-to-wafer bonding (the approach used in image sensors and YMTC’s NAND), Besi dominant in die/chip-to-wafer bonding (more relevant to HBM and logic stacking). Applied Materials holds a strategic equity stake in Besi and partners closely with it on integrated hybrid bonding platforms. Tokyo Electron, ASMPT, SUSS MicroTec, and Kulicke & Soffa round out the leading tier. A delayed HBM ramp means these suppliers’ HBM-specific hybrid bonding tool orders shift later in time, though demand from advanced logic and NAND roadmaps elsewhere continues on its own, separate timeline.

Summary

Bonding is the process of packaging chips, physically and electrically joining dies together. SK Hynix relies on its mature, proprietary MR-MUF process (solder plus epoxy); Samsung has used thermo-compression bonding but is now planning a partial move to hybrid bonding (direct copper fusion, no solder) starting at 16-high HBM4E. Hybrid bonding is the clear long-term future because it enables finer pitch, thinner effective stacks, and much better cooling, and it’s far from unproven, having run in CMOS image sensors since 2010 and in YMTC’s Xtacking NAND since 2018 to 2019. But scaling it reliably across sixteen-plus memory layers at commercial yield is a much harder problem than doing it once, and a JEDEC height-limit relaxation plus slower-than-expected demand for very tall stacks removed some of the urgency to rush it. So SK Hynix pushed full adoption from HBM4E to HBM5 (roughly 2029 to 2030). That shifts the timing of demand for equipment leaders like EV Group, Besi, and Applied Materials.

DNA’s four-letter alphabet: A, T, C, and G, repurposed to hold our data instead of biology’s

That’s the part I find genuinely interesting. We didn’t invent the storage medium. We’re borrowing one that evolution already optimized, and repurposing its four-letter alphabet (A, T, C, G) to hold our own information instead of biology’s.

How the Process Actually Works

None of this happens by accident, and none of it involves a fab. Here’s the pipeline, step by step:

1. Encoding. Your file, whatever it is, starts as binary: ones and zeros. Software translates that binary string into DNA’s four-letter alphabet, A, T, C, and G, using an encoding scheme built to avoid patterns that are hard for DNA to hold reliably (long repeats of the same letter, for instance, tend to cause errors).

2. Synthesis, meaning growing the DNA in the lab. This is the step people mean when they say DNA is “grown.” A synthesizer builds each strand one base at a time, chemically bonding one letter after another in the exact order the encoding step specified. It’s not grown the way a plant grows. It’s built, base by base, by machine, the same class of process the genomics industry already uses to manufacture synthetic DNA for research. This step is also the slowest and most expensive part of the whole pipeline, and it’s the main reason DNA storage isn’t commercially competitive yet.

3. Storage. Once synthesized, the DNA strands are dried down and often encapsulated, sometimes in silica, to protect them from moisture, heat, and light. In that state, sealed in something roughly the size of a vial, the data can sit for centuries with no power and no maintenance.

4. Retrieval. To pull data back out, you don’t have to read the entire archive. Short DNA “primers” act like a search key, using a lab technique called PCR to selectively copy and pull out just the strands that correspond to the file you want, out of a pool that might hold millions of unrelated sequences.

5. Sequencing, meaning reading the DNA. The retrieved strands are run through a DNA sequencer, which identifies the order of bases in each one. This is the cheapest and fastest step in the pipeline today, mostly because decades of genomics investment already drove sequencing costs down.

6. Decoding. Software reverses step one, translating the sequenced A-T-C-G string back into binary, running error correction to fix any bases that got misread or dropped along the way, and reassembling your original file.

The six-step DNA storage pipeline. Synthesis and retrieval are the real-world bottlenecks.

Six steps, and the two bottlenecks are the first and last real-world ones: synthesis is slow and costly, and retrieval still takes hours rather than milliseconds. Everything in the middle, the actual storage, is the part that already works better than anything silicon can offer.

Every storage medium I write about has a decay clock. Tape degrades. SSDs lose charge. Even the most robust NAND cell has a finite retention window before it needs a refresh cycle. DNA, kept cool, dark, and dry, can remain intact for centuries. Researchers have already pulled readable sequence out of specimens tens of thousands of years old. A storage medium that outlives the civilization that wrote to it isn’t a spec bump. It’s a category nothing in the semiconductor world can touch, because silicon was never built for millennia. It was built for a refresh cycle measured in years.

Density comparison across storage media

What’s Actually Happening Right Now

Make no mistake, this is still largely a lab curiosity. But it’s a lab curiosity with real hardware behind it now, and that’s worth sitting with. Atlas Data Storage, spun out of Twist Bioscience, has launched a synthetic DNA storage system that holds roughly a thousand times more data than traditional magnetic tape, and it’s aimed squarely at the kind of archives nobody wants to lose: family photos, scientific records, corporate history, the master copies of films and music. A separate team at the University of Missouri has gone further and built something closer to a rewritable drive, using a nanopore sensor that reads DNA sequences as they pass through it and translates the molecular signal straight back into ones and zeros.

The field has also stopped being purely a density story. The real progress through 2026 has been in retrieval, error correction, and manufacturability, not just theoretical density or millennia-scale stability claims. Selective access, meaning pulling one specific file out of a molecular soup without reading the whole pool, has moved from theory to demonstrated capability across sequence sets spanning millions of individual strands. That matters, because a storage medium nobody can search through fast enough isn’t a storage medium. It’s a vault with the door welded shut.

The Honest Caveat, Because I Always Give You One

None of this is close to replacing your SSD, and it isn’t going to. Writing data into DNA still costs orders of magnitude more than writing it to tape or flash, and reading it back can take hours, not milliseconds. Storing one megabyte in DNA today costs more than a million times what it costs on an SSD, and more than two and a half million times what it costs on magnetic tape, which is still the archival gold standard. Synthesis, the actual writing of DNA strands, remains the real bottleneck. Reading has gotten cheap thanks to the genomics industry. Writing has not caught up.

So this isn’t a memory tier that competes with HBM or displaces enterprise SSDs. It’s something else: a medium built for the data we can’t afford to lose and will never need to touch again in a hurry. Deep archive, not working memory.

Why I Keep Coming Back to This

I spend most of my working hours thinking about how to move electrons through smaller and smaller structures a little faster each year. DNA storage is a reminder that the densest, most durable information medium ever discovered wasn’t engineered by anyone. It was already sitting inside every cell of every living thing, doing this job for free, for four billion years, before anyone thought to ask it to hold something other than a genome.

That’s not an investment thesis. It’s just one of those ideas that makes the whole field feel a little bigger than a wafer map.

This has a name, and it’s older than the semiconductor industry

Supply chain economists call it the bullwhip effect. The idea dates back to Forrester’s work on industrial dynamics in the late 1950s, but the version most people know comes from a Procter & Gamble study on diaper demand. P&G noticed that retail sales of Pampers were remarkably steady, babies use diapers at a constant rate, but P&G’s own orders to its raw material supplier, 3M, swung wildly. Every layer of the supply chain was amplifying a signal that barely existed at the source.

The mechanism is simple. Each link in the chain doesn’t see real end demand. It only sees the order coming from the link below it, plus its own forecast of the future, plus a safety margin against being caught short. Add those together across several layers and a small, steady demand signal turns into a large, volatile one by the time it reaches the manufacturer.

Nobody in the chain is lying. Everybody is just protecting themselves against the layer below them being wrong.

Illustrative: a steady end-demand signal amplifies at each layer of the supply chain.

A long-term agreement doesn’t remove this mechanism. It just moves where the distortion shows up. Instead of arriving as a canceled order, it arrives as inventory sitting in a warehouse that was contracted for, paid for, and not needed yet.

Why fabs are the worst-case version of this problem

A 2025 NBER working paper by Leng, Liu, Ren, and Tsyvinski built a model of exactly this dynamic for industries with long production lead times. Their finding: when a sector takes a long time to build capacity, producers can’t react to today’s demand, they can only react to what they predicted demand would be when they started building. That time lag is what turns an ordinary demand shift into a pronounced bullwhip further up the chain.

Memory fabs are close to the textbook case. AMD’s CEO said publicly during the last chip shortage that standing up a new plant takes 18 to 24 months, sometimes longer. A capacity decision made today, LTA or not, is a bet on what demand looks like two years from now. The contract doesn’t shorten that lag. It just commits both sides to it in writing.

During the 2021-2022 chip shortage, the “lock in now” reflex showed up across the broader semiconductor industry, not just in memory. NXP, which makes automotive and industrial logic and analog chips, not DRAM or HBM, said at the time that customers wanted multi-year, non-cancellable, non-returnable contracts, some asking for two years of visibility. The logic was the same one driving today’s memory LTAs: secure supply now, at a fixed price, before conditions get worse. Worth being precise here, that’s a different product category than memory. It’s evidence of a recurring instinct across the chip industry during shortages, not a memory-specific precedent.

The more relevant precedent is what happened in memory itself. Samsung, SK Hynix, and Micron ramped DRAM and NAND capacity through 2021 and 2022 to meet what looked like durable demand. By 2023, memory prices had fallen roughly 40 percent as that demand cooled faster than the new capacity could be unwound. The three largest memory makers ended up sitting on excess inventory and cutting prices to move it.

This wasn’t primarily an LTA story, the mismatch came from capacity planning outrunning demand, not contracts specifically breaking down. But it’s the direct, memory-specific version of the point: capacity and supply commitments made at the peak of a shortage did not prevent the correction that followed. The chips still had to land somewhere real demand existed, and when it didn’t, the industry ate the difference regardless of what had been signed or planned a year earlier.

Is it already visible in this cycle too?

Not clearly. But there mihgt be cautions. TrendForce’s own July 2026 pricing note said server CPU shortages have slowed system assembly at U.S. cloud providers, which has led to a buildup of DRAM inventory, and that even CSPs with supply already secured have a strong incentive to keep building inventory ahead of an expected 2027 shortage. That’s precautionary ordering happening in real time, on top of contracts that were supposed to remove the need for it.

My take

An LTA is a claim on future output. It was never a guarantee that the output gets used on schedule. The bullwhip effect doesn’t care whether the order came from a spot buyer or a five-year contract holder, it amplifies whatever gap opens up between what was planned and what actually shows up in demand. Long lead times make that gap wider, not narrower. We’ve watched this exact mechanism play out in this exact industry within the last five years. The contracts changed. The outcome didn’t.

This cycle might turn out differently. Memory shortages could run long, and the industry could see years of real prosperity on the back of AI demand. That’s a separate question from whether an LTA is the right thing to point to as reassurance. It isn’t. It never was.

Here’s the actual sentence, from SemiAnalysis, hedges intact: “Market chatter suggests Google is working with AMD on a TPU project in the v10 generation.” Market chatter. Not a confirmed design win. Not a termination notice to Broadcom. Not even a signed contract. A rumor about a chip generation that’s still two to three years from mass production. Worth taking seriously. Worth understanding why it’s technically plausible. Not remotely the same thing as Broadcom getting shown the door.

I’ve been asked a lot of variations of “so does Broadcom even matter anymore” over the past week, so let me lay out where I’ve landed after going through this properly.

1. Broadcom isn’t going anywhere. The contract says so.

Start with the thing that actually got signed, because it’s the part everyone skipped past to get to the AMD headline. In March 2026, Broadcom and Google put pen to paper on a five-year cooperation agreement spanning four TPU generations, v8 through v11, with revenue visibility extending out to 2031. That’s not a company hedging its bets on a partner it’s trying to phase out. That’s a multi-generation commitment.

Google didn’t build its custom silicon program on a whim, and it didn’t pick Broadcom by accident either. This is a relationship that goes back to 2015, when Google needed a partner with deep expertise in high-speed silicon design and TSMC process technology, and Broadcom’s networking chip division fit the bill. Seven TPU generations later, that expertise compounds. Broadcom knows Google’s design methodology, its verification flow, its packaging requirements, in a way no new entrant walks in the door already knowing. Switching an incumbent ASIC partner isn’t like switching a cloud vendor. It’s closer to a multi-year restart, and Google just signed a document that says it isn’t interested in one, at least not for the core of the relationship.

So no, Google isn’t ditching Broadcom. The five-year deal is the floor under this entire conversation, and everything else needs to be read against that floor, not instead of it.

2. Diversification is real, and Broadcom said so itself.

None of that means Broadcom keeps 100% of Google’s wallet forever, and it would be dishonest to pretend otherwise. On the June 3 earnings call, Hock Tan told the Street directly that Google is going to use multiple chip suppliers going forward. That’s Broadcom’s own CEO, not an analyst’s inference, not a leaked memo. When your own management confirms a competitor is in the tent, you don’t get to wave it away as noise.

And this isn’t hypothetical. MediaTek is already there. The TPU v9 program runs on a dual-track split: Broadcom holds the training-focused SKU, MediaTek has picked up an inference-focused SKU, supplying its own SerDes I/O die and packaging work. Some of the sell-side coverage has framed this more aggressively, arguing MediaTek is actually becoming Google’s lead supplier rather than a junior partner, and Broadcom’s own admission that Google is “seeking to introduce other chip suppliers” gives that argument some teeth. The analyst community is split on how far this goes. Morgan Stanley thinks Broadcom holds around 80% share long term and calls talk of major displacement premature. Macquarie has a much steeper model, Broadcom’s share of Alphabet’s TPU revenue sliding from roughly 95% today to 65% by 2028. Nobody on either side disputes the direction. The argument is entirely about how fast and how far.

Point being, if AMD does end up with a role on v10, it’s not a shock development. It’s the third data point in a pattern Google has already been running for at least a year, and that Broadcom has already told investors to expect.

3. AMD isn’t a random name here. The technical fit is specific.

This is the part that got flattened the most in the retail commentary, so it’s worth actually walking through, because it’s more interesting than “AMD wants in on AI chips too.”

The rumored draw isn’t AMD building a TPU. It’s AMD solving a specific architectural problem Google is reportedly running into with reinforcement learning workloads. Today’s TPU setup pairs the accelerator with a separate host CPU, connected over the regular datacenter network. That’s fine for large batched training runs, but RL loops don’t look like that. They’re bursty and tightly interleaved: simulate an environment, compute a reward, update a policy, repeat, fast, over and over. Every one of those round trips between the CPU doing the environment work and the TPU doing the compute pays a network latency tax. At RL’s iteration speed, that tax adds up in a way it doesn’t for a single long training pass.

The fix is putting the CPU on the same package as the accelerator, so that round trip becomes a die-to-die hop instead of a network hop. And this is exactly the kind of problem AMD has already solved, for a different customer, which is itself: the MI300A chip integrates Zen CPU cores and GPU compute chiplets on one package, sharing unified memory, using hybrid bonding they’d already proven out with 3D V-Cache. That’s not a paper design. That’s shipping silicon.

AMD also isn’t borrowing anyone else’s interconnect IP to do this. Infinity Fabric is theirs, built in-house since the early EPYC days, with two tiers depending on the distance the signal needs to travel: a short, power-efficient link for in-package chiplet communication, and a separate one for longer socket-to-socket hops. Combine that with genuinely competitive x86 CPU cores, and AMD is bringing two things to the table that neither Google nor Broadcom currently has in combination: real general-purpose CPU IP, and proven experience physically stacking that CPU IP next to accelerator compute in one package.

Now, the honest caveat. MI300A works because AMD controls both halves of the bond, its own CPU chiplet and its own GPU chiplet. Bonding a Zen chiplet onto a third-party compute die designed by Google is a materially different integration problem, one AMD has never actually done for an outside customer. So the rumor is plausible and well-motivated on the technical merits. It is not the same thing as proven or easy. Worth being precise about that distinction, because SemiAnalysis was.

4. The pie is growing fast enough that this isn’t really a zero-sum fight.

Step back from the supplier-by-supplier scorekeeping for a second, because I think it’s the wrong frame for where this market actually is right now.

Broadcom is guiding to more than $100 billion in AI semiconductor revenue by fiscal 2027, up from an already-massive base, backed by a $73 billion order backlog. Custom ASIC shipments across the whole industry are projected to grow nearly 45% this year, roughly three times the growth rate of merchant GPUs. Google alone is reportedly looking at ordering somewhere between 12 and 15 million TPU v9 units by 2028, a volume that starts to rival Nvidia’s own GPU shipments. Demand at that scale doesn’t get satisfied by one vendor’s factory capacity anyway. Google is even said to be evaluating Intel Foundry as an additional packaging source, entirely separate from the Broadcom-versus-MediaTek-versus-AMD question, purely because the volume is too big for one supply chain.

When total demand is expanding at that pace, a supplier’s percentage share and a supplier’s dollar revenue can move in completely opposite directions, and that’s exactly what’s happening here. Broadcom’s share of Google’s TPU wallet can compress from something like 95% toward 65-80% over the next couple of years, depending on whose model you believe, while Broadcom’s absolute AI revenue from Google still grows, because the total pool it’s taking a smaller slice of has gotten so much bigger. That’s not a company losing a customer. That’s a customer that needs more capacity than any single vendor can responsibly provide, spreading the load the way any smart buyer would once its order size gets large enough.

Where that leaves things

Broadcom stays the incumbent and, on every read I’ve seen, keeps the majority of TPU volume for the foreseeable future, underwritten by a contract that runs through v11. MediaTek’s role is real and growing, not speculative. AMD’s potential role is specific, technically well-reasoned, and still unconfirmed, tied to a chip generation that’s likely two to three years out. And the whole conversation is happening against a backdrop where the market itself is expanding fast enough that everyone involved can plausibly grow in absolute terms even as the shares get redivided.

The headline version of this story, Broadcom loses TPU to AMD, is wrong on the facts and wrong on the framing. The real story is less dramatic and more interesting: a hyperscaler with enough volume to need more than one supplier, doing exactly what you’d expect a company managing that kind of scale to do.

Imagine someone tells you AI built the London Bridge in a month. Fed it satellite imagery of the Thames, load requirements, traffic projections. Four weeks later: a finished bridge, cars driving across it.

You’d know that’s not what happened. Not because AI can’t do impressive things with bridge design. It can generate a structural plan, run load simulations, optimize a truss geometry against wind and weight in a fraction of the time an engineering firm would take by hand. But steel has to get forged. Piers have to get sunk into riverbed. Girders get lifted and bolted by people standing on scaffolding in the rain, and that part doesn’t compress just because the planning did. A month gets you drawings. It doesn’t get you a bridge.

That intuition disappears the moment the structure is a chip instead of a bridge. “AI designed a chip” gets repeated like the whole distance between concept and working silicon collapsed into a weekend of inference. It didn’t. What actually happened with OpenAI and Broadcom’s Jalapeño, announced June 2026, is the honest version of the bridge story. The nine months everyone quotes covers initial design to tape out, not the spec and architecture work that came before it and not the manufacturing and validation that comes after tapeout. Inside that window, AI compressed specific stages of planning and checking.

Most of the bridge already existed

Here’s the part the “AI compressed nine months” framing quietly skips: a large share of Jalapeño wasn’t designed from scratch by anyone, human or AI, in those nine months at all.

Broadcom doesn’t build custom ASICs starting from a blank canvas. It runs an industrial parts catalog built over a decade, across five process node generations. Silicon proven SerDes running at 100 to 200G. HBM PHY and controller IP. Chiplet to chiplet interconnect. Full advanced packaging flows, CoWoS and its own patented chip to chip tech. This stuff has already been through tape out, already been through silicon validation, already had its bugs found and fixed on someone else’s chip. Broadcom controls something like 70 to 80 percent of the custom AI ASIC market for exactly this reason: it hands a new customer a base design where the hardest, highest risk blocks are already proven. The company runs roughly 120 tape outs a year across all its platforms. You don’t hit that throughput by redesigning SerDes and HBM interfaces from zero every time. You hit it by not doing that.

So the math on the nine months changes. The genuinely novel work wasn’t the whole chip, it was th logic layered on top of an already proven base, the new logic covering mainly OpenAI’s inference specific architecture, kernels, memory movement patterns. When OpenAI and Broadcom said AI accelerated “parts of the design and optimization process,” they were describing an already smaller slice of the problem than the headlines implied. And to be clear, reusing proven IP isn’t a shortcut anyone should feel sheepish about. It’s what a disciplined team is supposed to do, and it’s a big reason the timeline was survivable at all. But an honest accounting has three inputs, not two: AI accelerated work, human judgment, and a decade of silicon proven IP that nobody built in nine months because it didn’t need building again.

The flow, stage by stage

Now the actual flow, with realistic time weighting. This is where “AI can’t build the bridge in a month” gets its teeth.

One scoping note before the list, because it matters for how you read the nine months. OpenAI and Broadcom’s own number covers initial design to tape out. That’s RTL onward. Specification and architecture, the stage below, sits before that window starts, not inside it. Fold spec time into the nine months and you’re misreading what got compressed.

Specification and architecture — roughly 3 to 6 months, outside the nine month window. Engineers define functional requirements, performance targets, power budget. For Jalapeño that meant OpenAI’s own engineers defining the chip around its actual kernels and serving behavior. Short in calendar time relative to what follows. Disproportionately consequential, because every downstream decision inherits its mistakes. AI helps here as a research tool. The tradeoff calls still get made by people.

RTL design — at best 4 to 6months. Engineers write the register transfer level code describing the chip’s logic. Roughly 10 to 20 percent of total design cycle time, by most industry benchmarks. This is a stage where AI has made real, measurable inroads, agentic coding tools now generate substantial RTL from a spec and iterate against it faster than a human writing it by hand.

Verification — roughly 8 to 14 months, running largely in parallel with the RTL design phase. Before anything gets fabricated, the design has to survive being checked against nearly every way it could fail. This is the biggest time sink in the entire flow, not close. Most ASIC projects spend 60 to 90 percent of frontend effort here. It’s also where AI is earning the most real, quantifiable speedup. Synopsys’s autonomous verification agent claims up to 50 times faster time to validated RTL with better coverage. Cadence’s ChipStack is reported to cut RTL validation from five weeks down to days. Verification is combinatorially large and exhaustively checkable, which is exactly the kind of problem where a model running millions of automated passes has a real edge over a person iterating by hand. This is the actual engine behind the nine month number. Not the RTL. This.

Synthesis — weeks, folded into the RTL to physical design handoff. The verified RTL becomes a gate level netlist mapped to the foundry’s standard cell library. Largely automated already. Not a bottleneck.

Physical design — roughly 5 to 9 months. The logical design becomes a geometric layout. Floorplanning, placement, clock tree synthesis, routing, power planning, all while closing timing, power, and thermal targets that fight each other constantly. Widely considered the hardest, most iterative part of the flow, because a decision made here can force you back to an earlier stage entirely. Autonomous tools are pushing in, but the industry’s own language gives it away: EDA vendors describe their tools on the self driving car’s L1 to L5 autonomy scale, and in 2026 the leaders are pitching Level 4, not full autonomy, for the hardest parts of physical closure.

Signoff — roughly 1 to 2 months, the tail end of the physical design window above. Exhaustive checks before the layout goes anywhere near a mask set. Design rule checks against the foundry’s manufacturing rules. Layout versus schematic checks. Electromigration and ESD checks. Timing signoff with extracted parasitics. IR drop analysis. A mistake caught here costs weeks. A mistake missed here costs a full re spin, months later, after the chip comes back from the fab and fails.

Tape out and fabrication — roughly 3 to 5 months. The signed off design ships to TSMC as a GDSII file. Fabrication runs several more months regardless of how fast the design phase moved: wafer processing, then packaging, then initial testing. No model touches this step. It’s industrial execution on equipment that took decades to mature, and it doesn’t care how fast your RTL got written.

Board level design — roughly 2 to 4 months, mostly parallel to the chip work. A finished die isn’t a product. It needs boards, racks, power delivery, signal integrity, thermal design for the full system, connectors, networking. This is where Celestica’s role in the Jalapeño program actually sits, separate from Broadcom’s chip level work. Its own discipline, with its own validation cycle.

Post silicon validation — roughly 3 to 6 months. Once packaged parts come back, engineers test the chip across real voltage, temperature, and workload conditions, not the conditions simulated before tape out. This is a different discipline from pre silicon verification. It’s physical reality against the model of reality, and it routinely finds problems no simulation caught, because real silicon has parasitics and process variation that models only approximate. Jalapeño’s engineering samples running lab workloads is this stage in progress. OpenAI has said final performance measurement is still ongoing. That matters more than the headlines gave it credit for.

Re spins — 2 to 4 months per cycle if one is needed, and it’s not clear yet whether one is. Rare for a complex chip to go from first tape out straight to volume without at least one more pass. A bug found in post silicon validation gets fixed with a metal only re spin if it’s cheap, changing only the upper interconnect layers, or a full re spin back through physical design and signoff if it’s not. Each cycle costs real months and real fabrication dollars. Nobody outside the program knows yet how many Jalapeño will need before “nine months to tape out” becomes “shipping at volume.”

Add it up and a large GPU class chip runs something like 24 to 36 months from spec to tape out, plus another handful of months for fab, packaging, and bring-up before anything ships. These are illustrative ranges, not a citable figure for any specific program, and actual timelines swing hard on team size, node maturity, and how much IP gets reused instead of built.

Why the bridge analogy holds

Line these up against the bridge and it tracks. AI accelerated verification and RTL generation are the software compressing months of load calculation into days, real, valuable, still just the planning phase. Physical design closure is the stage where engineers turn that plan into construction drawings accounting for the actual site. Signoff is the final inspection before anyone pours concrete. Fabrication, packaging, board integration, and post silicon validation are the actual pouring of concrete, the raising of steel, the stress testing of the finished span. Broadcom’s decade of packaging IP is the contractor’s existing inventory of prefabricated parts. TSMC’s fabs are the cranes and the crews, and their work takes the time it takes.

Until the robots show up

The honest caveat here is: not yet, and not until something functionally like construction worker robots exists, machines built for physical execution rather than planning and checking. In chip design that’s not a metaphor, it’s the direction the EDA industry is explicitly racing toward. The push to L5 autonomy is an attempt to build agents that don’t just generate and check a plan but drive physical closure decisions with less human hand holding. It isn’t there yet. And even the vendors pushing hardest frame the pitch around trusted automation inside production teams, not full removal of human judgment, because their actual moat is tight integration with decades of proprietary, silicon proven data. Not the model. If a general purpose model could run the whole flow, a frontier lab’s own models would already be doing it. They aren’t. The parts of chip design that need institutional memory, a process node’s specific quirks, a foundry’s specific design rules, why a certain clock tree topology blew up three generations ago, don’t live in training data. They live in the people who accumulated that memory the hard way. Right now it has to be handed to the model. It can’t yet be pulled out of one.

The discipline clause

Same risk as handing a construction crew a beautifully optimized blueprint and telling them to move twice as fast without checking anything. A verification agent running 50 times more test passes only helps if someone with real judgment set the correctness bar right and can catch the agent optimizing against the wrong thing. Strip that person out, and the same tools that compress a disciplined team’s schedule by 10x compress an undisciplined team’s path to an expensive re spin by roughly the same factor. The mistake a senior engineer’s gut used to catch on review four now sails through untouched. Just faster.

Bottom line

AI didn’t build the bridge in a month, and it didn’t design Jalapeño alone. It compressed the frontend planning and checking work, RTL and especially verification, inside a flow that still runs through physical design closure, signoff, fabrication, board level integration, and post silicon validation by expert humans and mature industrial infrastructure, sitting on a decade of Broadcom IP nobody had to redesign at all. That compression is real. It’ll keep compounding. What changes the story from here isn’t a faster model, it’s whether autonomy actually reaches physical closure and fabrication, and how many re spins Jalapeño needs before it’s actually shipping. Until both of those get answered, the teams that benefit are the ones with enough institutional memory and enough discipline to supply the judgment AI still can’t.

01 — WHAT HAPPENED TODAY

A preliminary MOU becomes a binding contract

On August 11, 2026, Sony Semiconductor Solutions and TSMC signed a definitive, legally binding agreement to establish a joint venture named Advanced Vision Semiconductor Manufacturing Corporation, closing out a process that began with a non-binding MOU back in May. The venture will sit inside Sony’s newly built fab in Koshi City, Kumamoto Prefecture, and target volume production in 2029.

Two things worth flagging before the headline number gets repeated uncritically: the widely-quoted “$6.3 billion” figure (¥1 trillion) is a Nikkei estimate that bundles in future capacity expansion contingent on Japanese government subsidy support that hasn’t been finalized. The disclosed, binding capital contribution in the definitive agreement is closer to ¥747 billion (~$4.7B). Second — Sony remains the sole controlling shareholder and consolidates the JV as a subsidiary; this is not a 50/50 merger of equals, and it isn’t Sony ceding control of its sensor business.

02 — THE LANDSCAPE

Two majors, two minors — and Sony isn’t close

The CMOS image sensor (CIS) market is a roughly $23-30 billion business growing high single digits through 2030, per Yole Group. It has a clean four-player structure: two majors that actually compete for premium smartphone sockets, and two minors that compete on cost, niche performance, or automotive volume rather than flagship share.

Sony’s lead is not a rounding error — it’s roughly 2.5x Samsung’s share and has been stable or growing for years, built on being first to nearly every major architectural advance: backside illumination, stacked sensors, and hybrid bonding. onsemi and OmniVision don’t really contest that lead; they compete for the mid-range, automotive, and cost-sensitive tiers Sony has less interest defending pixel-for-pixel.

03 — THE TECHNICAL CORE

A sensor is (at least) two dies. The JV touches one.

This is the detail most coverage of the JV gets wrong or glosses over. A modern stacked CIS is not a single chip — it’s two physically separate wafers, fabricated with entirely different process requirements, then bonded together.

Note: Some architectures add a third DRAM die for frame-buffer speed — a separate memory-tier discussion, not part of this JV.

Pixel die — stays 100% Sony

The photodiode array, the analog front-end, and Sony’s proprietary BSI and stacking know-how are the company’s actual moat — the reason its sensors lead on dynamic range and low-light performance. Nothing in the JV disclosure touches this layer. Sony designs it, and continues to fabricate it in-house.

Logic die — the JV’s actual subject

The logic/ISP layer handles readout, analog-to-digital conversion, and increasingly on-sensor AI inference. Sony has quietly bought this layer from TSMC for years already — 22/28nm and 12/16nm class, the same process tier running at TSMC’s existing JASM fab in Kumamoto. What’s new isn’t the relationship; it’s the structure: dedicated, co-located capacity inside Sony’s own fab, with TSMC as an equity partner sharing capex risk instead of a pure merchant-foundry customer relationship.

WHY NOT A LEADING-EDGE NODE

CIS logic doesn’t want 3nm. Bleeding-edge nodes optimize for logic density and switching speed at the cost of analog performance, transistor variability, and wafer cost — the wrong trade for a large-area, price-sensitive, ADC-heavy die. The “advanced node” language in most coverage is advanced relative to Sony’s historical in-house capability, not relative to TSMC’s leading edge. Don’t confuse the two in any modeling.

04 — THE OTHER HALF OF THE STORY

Samsung’s Apple win: second source, not displacement

The JV doesn’t exist in a vacuum. It’s the direct response to Samsung breaking Sony’s decade-plus exclusivity as Apple’s iPhone camera sensor supplier.7

Why Apple actually did it

Two drivers, neither of which is really a verdict on Sony’s technology: (1) delivery delays from Sony in 2023-2024 disrupted Apple’s production schedule and pushed a classic supply-chain diversification response, and (2) tariff and localization pressure — Sony has no U.S. manufacturing footprint, while Samsung’s Austin line lets Apple hedge exposure to semiconductor tariffs while checking a “made in America” box.

Is Sony threatened?

Not on the scoreboard that matters most — global share. Sony’s ~50% lead is described by multiple industry analysts as effectively unassailable near-term; Android flagships, automotive, security, and the bulk of Apple’s own sensor volume are unlikely to move meaningfully by 2029. What’s actually at risk is narrower and more structural: pricing leverage and exclusivity premium on Sony’s single most prestigious account. Moving from sole-source to dual-source with Apple doesn’t cost Sony units in the near term, but it costs Sony negotiating power, and it removes the “nobody else can do this” story that justified premium pricing.

05 — IMPLICATIONS

What this actually changes, ranked by how much it matters

1. Samsung’s real threat isn’t sensors — it’s the bundle

Samsung is the only player that owns design, foundry, and packaging simultaneously. The JV specifically neutralizes the piece of that bundle Sony lacked: guaranteed access to competitive logic fabrication. It’s a defensive move aimed at preventing Samsung’s structural advantage from compounding over the next product cycle, not a response to an immediate share loss.

2. Sony is converging toward the OmniVision/Chinese fabless model — at the top of the market

OmniVision, SmartSens, and GalaxyCore already lease TSMC and other foundries for their logic layers. Sony isn’t inventing a new operating model here; it’s applying the fabless-for-logic playbook that its lower-tier competitors used for cost and speed, but backed by far greater design R&D and Apple-tier customer relationships.

3. onsemi is a secondary, not primary, casualty

onsemi doesn’t compete with Sony in mobile. But the JV’s explicit targeting of automotive and “physical AI” — a segment where onsemi has built its moat via global-shutter ADAS sensors — raises the technology bar in the one arena onsemi had mostly to itself.

4. Watch the Austin allocation number, not the global share number

The single most important data point for this thesis over the next 24 months isn’t Sony’s global CIS share — it’s what fraction of iPhone sensor volume Samsung’s Austin line actually captures once qualification is complete. A stable minority allocation confirms this was tariff-hedging. A growing allocation confirms Samsung’s bundle is becoming a credible full alternative.

06 — SUMMARY

The bottom line

Sony isn’t losing its lead — it’s protecting the one weakness that could have let Samsung’s vertical integration compound into a real threat. The JV formalizes a logic-die relationship with TSMC that already existed informally, doesn’t touch Sony’s core pixel IP, and almost certainly won’t run on leading-edge nodes given CIS logic’s analog and cost requirements. Samsung’s Apple win is real and structurally meaningful for pricing leverage, but it’s a second-source diversification driven by tariffs and delivery risk — not evidence that Sony’s sensor technology has been leapfrogged. The company most exposed to this reshaping isn’t Sony; it’s the assumption that Sony’s dominance was ever purely a manufacturing story rather than a design one.

The answer is probably somewhere in between.

HBF is real. The capacity problem it addresses is real. And the economics could be compelling. But the technology now has to prove something much harder than technical feasibility: that putting NAND much closer to the accelerator creates enough system-level value to justify another memory tier in an ecosystem already developing HBM, CXL memory and NVMe-based context storage.

Here’s what’s genuinely good about HBF, what’s genuinely unresolved, and what should worry anyone betting on it becoming infrastructure rather than a niche.

What HBF actually is, and why it matters

Strip away the marketing and HBF is NAND flash packaged as a high-bandwidth memory tier rather than a conventional SSD. The specification supports 8-high and 16-high NAND stacks, with capacities of up to 512GB per package and bandwidth grades ranging from roughly 0.4 TB/s to 3.0 TB/s. HBF uses a logic/base die and connects to the host through UCIe, allowing the flash stack to sit much closer to the accelerator than conventional storage.

That distinction matters. HBF isn’t trying to turn NAND into DRAM. It is trying to exploit the fact that many AI workloads increasingly need far more capacity than HBM can economically provide, while not every byte of data needs HBM-class latency.

HBM is extraordinarily fast but expensive and physically constrained. Conventional SSDs provide enormous capacity but are separated from the accelerator by controllers, protocols and system-level I/O paths. HBF is intended to occupy the space between them: dramatically more capacity than HBM, much higher bandwidth than conventional storage, and physically closer to the compute engine.

The chart above captures the basic proposition. There is no magic memory that is simultaneously enormous, cheap, extremely fast and extremely low latency. Every tier is a trade-off. HBF deliberately gives up latency and endurance relative to DRAM in exchange for dramatically more capacity.

And that trade could make sense for AI.

The Good

The standardization timeline is genuinely fast. Six months from consortium formation to a published open specification is quick by memory-industry standards. More importantly, the specification is no longer just a concept: the industry now has a defined target around stack height, capacity, bandwidth and UCIe connectivity.

That doesn’t guarantee adoption, but it moves HBF from an interesting technology proposal toward something hardware and software engineers can actually design around.

The capacity number is real, and it is large. A 512GB HBF package is roughly eight times the capacity of a 64GB HBM4 stack, depending on the HBM configuration being compared. That’s not an incremental improvement; it is a different class of capacity.

That matters for workloads such as large model weights, embeddings, retrieval datasets and other read-heavy data structures that increasingly don’t fit economically into local HBM.

The important point is that these workloads don’t necessarily need every byte to have HBM latency. They need enough bandwidth, enough locality and enough capacity to keep the accelerator productive.

The economics could be HBF’s killer feature. This is still unproven, because no one is shipping HBF at volume yet. But NAND has a fundamentally different cost-per-bit structure from DRAM. If HBF can deliver hundreds of gigabytes of useful, high-bandwidth memory close to the accelerator without approaching HBM’s cost per bit, the resulting capacity expansion could be substantial.

That is particularly attractive as AI models become increasingly memory-bound.

Google’s involvement is the strongest signal of real intent. Google joining the effort early is meaningful because hyperscalers ultimately determine which memory architectures become infrastructure. It suggests that at least one major AI platform provider believes the capacity problem is sufficiently important to investigate a new memory tier.

Tenstorrent’s participation is also useful evidence, although its commercial weight is still pretty small.

The important caveat is that participation in a standards effort is not the same thing as a production commitment.

And HBF may have a more interesting AI workload than simply “storage near the GPU.”

This is where the story gets more interesting.

Recent research specifically examining HBF for KV cache argues that KV cache can exhibit a write-once/read-many pattern, particularly in long-context inference. That means NAND endurance does not automatically rule KV cache out.

Other recent research has gone further, showing that architectures co-designed around HBF can improve throughput and energy efficiency by using HBF for both model weights and KV cache while keeping latency-sensitive data in HBM.

In other words, the bull case for HBF is not simply “NAND is cheaper.”

It is:

AI workloads are becoming increasingly heterogeneous, and some of the data growing fastest does not necessarily require HBM-class latency.

That’s a much more compelling proposition.

The Bad

The tradeoffs are real, and they define exactly how difficult HBF will be to integrate.

The biggest problem isn’t simply NAND endurance. It’s latency and access granularity.

HBF can provide impressive sequential bandwidth, but NAND still has much higher access latency than DRAM. And high-bandwidth flash architectures typically work with much larger access granularities than conventional GPU memory.

That creates a fundamental architectural problem.

A GPU does not simply ask for “memory bandwidth.” Its workloads generate enormous numbers of fine-grained accesses, and moving a large flash block when only a small portion is required can waste much of HBF’s headline bandwidth.

Recent research on large-granularity memory systems, including HBF-like architectures, shows that poor data layout and access granularity can produce severe performance degradation for tiled matrix operations.

Another 2026 study of HBF-based LLM inference identifies high access latency, low bandwidth utilization and the lack of mature heterogeneous resource management as major integration challenges.

That is a much more serious technical challenge than simply asking whether NAND can survive enough writes.

KV cache is therefore neither an obvious win nor an obvious failure.

Hot, actively changing KV cache remains a poor fit for flash. But cold or persistent KV cache can be much more attractive, especially when the same context is reused repeatedly.

The real question is workload placement.

HBF probably won’t replace HBM. It may instead become useful for the portion of the working set that is too large for HBM but too performance-sensitive for conventional storage.

That distinction makes HBF potentially valuable, but also makes the addressable market narrower than the raw 512GB-per-package headline suggests.

Another issue is that HBF is arriving into an increasingly crowded memory hierarchy. NVIDIA is already attacking the same underlying capacity problem from the storage side.Its CMX Context Memory Storage architecture uses BlueField-4 and storage infrastructure to manage and share KV cache across AI compute and context-memory nodes. NVIDIA’s software stack explicitly turns Ethernet-attached flash into a pod-level cache tier.

At the other end of the middle tier, CXL memory is emerging as another answer. CXL can provide substantially more capacity than local accelerator memory while retaining DRAM-class characteristics, making it attractive for warm data and shared memory.

So HBF doesn’t simply need to beat SSDs. It needs to demonstrate that on-package NAND provides enough incremental performance over NVMe and enough cost/capacity advantage over DRAM/CXL to justify a new architecture.

That’s a much higher bar.

Moreover. The economics remain unproven. A specification tells us almost nothing about eventual yield, packaging cost, thermal behavior, controller complexity or software-development costs.

HBF also needs advanced packaging and high-density integration, both of which are increasingly strategic bottlenecks across the semiconductor industry.

But the important question is not simply whether HBF competes directly for the same CoWoS capacity as HBM. The actual packaging route and economics will determine that.

The safer conclusion is simpler:

HBF has to prove that its packaging and integration cost doesn’t erase the economic advantage of NAND.

Until volume production exists, that remains an open question.

The Ugly

This is the part that should worry anyone treating HBF as a foregone conclusion.

The customer list is still thin.

Google is a meaningful participant. Tenstorrent is another useful data point.

But there is currently no publicly confirmed production commitment from NVIDIA, AMD, Intel, Samsung, Micron or Kioxia to adopt HBF. Contemporary reporting also notes that the major accelerator and memory players outside the initial group have not committed to the technology.

That doesn’t mean they oppose HBF. It means the industry has not yet demonstrated that HBF is sufficiently compelling to force its way into existing AI architectures. And that distinction matters.

NVIDIA hasn’t signed on, and it isn’t obvious that it needs to.

NVIDIA already has multiple ways to attack the memory-capacity problem.

Its CMX architecture is pushing KV-cache and context data toward NVMe-based storage at rack scale.

CXL memory is also moving toward the warm-memory tier.

For NVIDIA to adopt HBF, the company would need a concrete workload where putting NAND physically next to the accelerator creates enough performance or efficiency improvement to justify another memory type.

That is possible.

But NVIDIA doesn’t need HBF simply because HBF exists. It needs HBF if HBF is materially better for a workload that matters.

Samsung’s absence is notable, but the reason is harder to establish.

Samsung already has substantial activity across CXL memory, memory pooling, PIM, HBM and NAND-based AI storage.

That gives it multiple ways to address the same underlying problem without necessarily adopting a standard developed around SK hynix and SanDisk.

It would therefore be more accurate to say that Samsung has competing strategic options, rather than claiming that Samsung is deliberately sitting HBF out because of those alternatives.

The distinction matters: the first is observable; the second is inference.

Micron is another example of why the competitive picture is fluid. There has been no commitment from Micron on HBF.

One real hyperscaler does not make a standard.This is ultimately HBF’s biggest commercial risk.The technology can work. The capacity proposition is compelling. The bandwidth numbers are real. The AI workload is real. But standards win when enough customers decide that they cannot afford not to support them.

Right now, HBF has a strong founding pair, a hyperscaler participant and an AI-chip participant. What it does not yet have is broad evidence that the major accelerator vendors, memory suppliers and system builders believe HBF is necessary.

That is the gap between a technical standard and an industry standard.

And it is also why projections of HBF appearing in NVIDIA, AMD or Google products in 2027–28 should be treated as forecasts, not commitments.

The bottom line

HBF is neither a gimmick nor an inevitable new layer of the AI memory hierarchy.

It is a credible attempt to solve a very real problem: AI systems increasingly need dramatically more memory capacity than can economically sit in HBM.

The technology’s strongest argument is not that NAND can somehow become DRAM.

It is that AI workloads are becoming heterogeneous enough that some data — model weights, embeddings, persistent context and potentially portions of KV cache — can trade latency for capacity.

That creates a potentially valuable middle ground: HBM for hot data,CXL/DRAM for warm data, HBF for large, bandwidth-hungry, relatively read-heavy data, NVMe/CMX for enormous, colder context and storage.

The bear case is equally clear.

HBF has to overcome coarse access granularity, endurance constraints, software complexity and the simple fact that the industry is already building alternative solutions.

NVIDIA’s CMX architecture is attacking the problem from the storage side. CXL is attacking it from the DRAM side. HBF has to prove that neither approach is good enough for a meaningful class of workloads.

That is the real test.

The next twelve months aren’t about whether HBF works.

They are about whether HBF can demonstrate enough system-level advantage that customers with working alternatives decide they need a new memory tier anyway.

If it can, HBF could become one of the most important architectural changes in AI memory after HBM.

If it can’t, it may remain what it is today: a very clever solution to a problem that the industry ultimately decides to solve another way.

A DRAM fab takes years to plan and build. A node ramps on a schedule measured in quarters. Wafer capacity, HBM stack yields, packaging bottlenecks: you can see almost all of it coming six to eighteen months out, straight from capex guidance and supplier roadmaps. Supply is, relatively speaking, a solved problem. Build a spreadsheet, be roughly right.

Demand is not that. The optimized AI architecture still hasn’t landed. Attention mechanisms are being rewritten as we speak. Quantization keeps finding new floors. MoE routing, KV-cache compression, speculative decoding, disaggregated prefill/decode: all of it is live and moving faster than any single “memory per token” model can track. Every quarter brings a technique that either shrinks the footprint of a token or expands how many tokens are worth generating in the first place. Both forces are large. Nobody has a validated model for which one wins.

Strip away the confidence in most research notes and what’s actually underneath every HBM demand forecast is a belief, a reasonable one, but a belief, that Jevons paradox holds. That cheaper tokens generate more total demand than they save in cost, so memory consumption keeps climbing even as efficiency improves. That single assumption is carrying an enormous amount of weight in every “structural shortage through 2028” call published this year. It deserves to be treated as the load-bearing variable it is, not a footnote.

Jevons holding isn’t the same as Jevons being proven

Jevons paradox isn’t a law of physics. It’s a claim about elasticity: usage has to grow faster in percentage terms than the resource gets cheaper, or the whole thing falls apart. It held for coal-fired steam power. It’s held for computing generally. It has also failed plenty of times, usually once a use case saturates and cheaper access stops unlocking anything genuinely new.

The evidence for it holding in AI right now is good. Reported token growth at the major platforms has run 4-7x a year, memory demand for serving that traffic has tracked closer to 40%, and that gap implies the industry is already banking roughly 30% a year of efficiency gains and still watching memory need explode. That’s real, it’s measurable, and it’s the strongest evidence anyone has that expanding use cases (e.g. longer context, agent chains, multi-step reasoning) are eating efficiency gains faster than they show up.

But “currently holding, with wide error bars” isn’t “guaranteed through 2028.” The honest version of this thesis says efficiency would need to accelerate well past its current measured pace to flip the balance, and there’s no clean evidence that’s about to happen. But there’s also nothing preventing it. Anyone building a multi-year shortage call on this assumption owes the reader that caveat up front, not buried three paragraphs from the end.

The reverse case is the one nobody’s modeling

If Jevons paradox means efficiency gains get reinvested into more demand than they save, the mirror image is what happens when they don’t. Efficiency improves, usage grows too, just not fast enough to offset it. So total consumption actually falls. Call it reverse Jevons.

This matters more than it sounds like it should, because it’s the one scenario pure supply-side analysis will never catch. Supply-side models treat the demand trajectory as a known input. Reverse Jevons looks like: KV-cache compression keeps clearing new thresholds, but instead of that headroom getting spent on longer context and bigger agent workloads, usage growth flattens out because task value stops scaling with token count as fast as cost falls, or enterprises start capping spend instead of letting it run. Memory bit-demand falls even as tokens processed keeps climbing, because bytes-per-token is winning the race against tokens-per-task.

Nobody catches this until it’s already sitting in the numbers. By then the capital’s already been deployed on the opposite bet.

What to actually watch

Capex guidance and hyperscaler earnings are lagging indicators. They’re self-reported, filtered through a supplier’s incentive to keep customers calm and a hyperscaler’s incentive to justify its own spend. Useful, but not early. Here’s what moves ahead of the consensus number.

The deceleration of the deceleration.

Headline growth prints 4x, 7x, whatever the current number is, hide the more important second derivative. What matters is whether the growth rate is decelerating across consecutive periods, not whether growth stays positive. One soft quarter means nothing. Two or three quarters running where the rate of change itself keeps falling is the earliest legitimate tell that elasticity is weakening.

Usage-capping language showing up in earnings calls.

Watch for the shift from “our customers keep using more” to “we’re helping customers optimize spend.” Per-task token budgets, tiered routing that defaults to a cheaper model unless a task explicitly needs more, rate-limiting language — all of it signals demand hitting a ceiling rather than expanding to meet falling cost. This shows up in transcripts before it shows up anywhere else.

Context utilization, not context capability.

Max supported context keeps growing: a million tokens and climbing. Average context actually used is a different number, and it’s the one that drives memory demand, not the max. If utilization plateaus while headline maximums keep rising, that’s a sign the long-context use case isn’t absorbing capacity the way aggregate demand models assume. Rarely disclosed cleanly, but worth digging out of vendor posts when it surfaces.

Memory-per-system, watched for its first real reversal.

Every GPU generation has shipped with more memory than the last, not marginally more, meaningfully more. That trend is probably the cleanest live proxy for whether the industry still believes memory-hungry use cases keep expanding. The first generation to cut system memory by design, not as a supply-constrained workaround like splitting prefill onto cheaper memory, would be the strongest direct signal available that someone closer to real demand than any analyst decided more memory wasn’t worth paying for.

Spot pricing against sold-out claims.

The most directly investable one on this list. Elevated pricing only holds if demand actually clears at that price. “Sold out through 2026” and “spot pricing is softening” can’t both stay true for long. Either the sold-out claims are options rather than locked commitments, or reported pull-through is running ahead of what’s actually being consumed. Track spot HBM3E/HBM4 pricing against supplier order-book language, quarter over quarter. It’s the closest thing to a real-time demand check that public data allows.

Compression clearing a threshold without a demand response.

There’s already a stated falsifier on the efficiency side: production KV-cache compression clearing a much higher ratio than today’s. The reverse-Jevons companion test is what happens after that clears. If compression jumps and memory-demand growth doesn’t reaccelerate off the back of it, no expansion in context length or batch size soaking up the freed capacity, that’s about as clean a confirmation as you’ll get that elasticity has weakened. It isolates the efficiency shock from the demand response in a way the growth headline never can.

The substitution risk underneath all of it

One more wrinkle, and it sits outside the Jevons framework entirely. Even if total AI compute demand grows exactly as Jevons paradox predicts, that says nothing about which memory technology captures the growth. The industry is already splitting hot-path memory across HBM and on-chip SRAM for decode-heavy workloads. If a real chunk of the token growth that’s “justifying” the paradox ends up routing through SRAM-based inference instead of GPU-plus-HBM stacks, you can have Jevons validated at the compute layer and simultaneously wrong at the HBM layer, volume up, HBM’s share of that volume down. Watching deployment volume of these alternative decode architectures over the next several quarters matters as much as any of the six signals above, because it’s the one variable that can decouple total AI growth from HBM-specific demand growth.

Bottom line

Supply is close to fully mapped: fab timelines, wafer capacity, yield curves, all forecastable years out. Demand isn’t, and treating Jevons paradox as a settled input rather than the biggest open variable in the whole model is the most common shortcut in HBM coverage right now. Growth-rate deceleration, usage-capping language, context utilization versus capability, a memory-per-system reversal, spot pricing versus order books, and the demand response to compression breakthroughs — these are the signals that show up before the lagging capex and earnings numbers confirm or break the thesis. Add architecture substitution on top and the honest position is: the HBM demand floor is well-supported by current evidence. It’s not a structural guarantee. Investors watching the capex chart alone will be the last to know if it starts to give.

Executive Summary

In October 2025, NVIDIA and Nokia announced a strategic partnership pairing a $1 billion NVIDIA equity investment (166 million shares at $6.01, a roughly 2.9% stake) with a joint technical roadmap to embed NVIDIA’s Grace CPU and Blackwell GPU compute directly into Nokia’s radio access network (RAN) products. The deal did two things at once: it handed Nokia a credibility and balance-sheet boost that sent the stock up over 20% in two sessions, and it planted NVIDIA’s flag in a market it has never owned — telecom infrastructure. Nine months later, at MWC and GTC 2026, the companies detailed ARC-Pro (Aerial RAN Computer Pro), a cell-site accelerated computing platform, and in July 2026 announced field results claiming a doubling of spectral throughput by 2028.

The strategic significance is bigger than the dollar amount. NVIDIA is trying to do to the RAN what it did to the data center: displace fixed-function, vendor-specific ASICs with a general-purpose, CUDA-programmable GPU platform, and capture the software and tooling layer (Aerial, CUDA-X) around it. Nokia is the willing first mover; Ericsson, its main rival, has explicitly declined to follow, betting instead on custom silicon and Intel Xeon. That divergence is the trade to watch.

1. Deal Structure

Thiw investment is explicitly tied to co-development, not a passive stake. NVIDIA gets a flagship telecom reference customer and a foothold for edge-AI inferencing demand; Nokia gets capital, a marquee technology partner, and — for a company that lost ground to Ericsson and Huawei in 5G — a new strategic narrative heading into the 6G standardization cycle (expected to conclude around 2029).

2. What NVIDIA Is Actually Doing — The Technical Layer

NVIDIA’s pitch is an extension of its core playbook: move a workload that currently runs on fixed-function or proprietary silicon onto a general-purpose, CUDA-programmable GPU, then own the software stack that sits on top. In the RAN, that workload is Layer 1 (L1) baseband processing — the computationally intensive signal-processing chain (channel coding, FFT/beamforming, MIMO detection, forward error correction) that has historically demanded custom ASICs or DSPs because of hard real-time latency budgets under one millisecond.

ARC-Pro hardware stack

• Grace CPU — a 72-core Arm-based CPU (NVIDIA’s own silicon, not licensed x86) handling control-plane and non-accelerated workloads, replacing the Intel Xeon that has dominated cloud-RAN deployments to date.

• Blackwell RTX PRO GPU — the accelerator doing the heavy L1 signal-processing math, positioned as capable of running RAN compute and spare-capacity AI inferencing on the same silicon.

• Mellanox ConnectX networking — NVIDIA’s own NIC/switch silicon (from the 2019–2020 Mellanox acquisition) providing the fronthaul/midhaul interconnect, notably displacing what would otherwise be a third-party networking vendor’s opportunity.

The critical architectural shift in ARC-Pro versus NVIDIA’s earlier ARC platform is that Nokia has committed to running L1 processing natively/inline on the GPU, with no separate look-aside accelerator card. That’s a meaningfully more aggressive integration than “a GPU assists a dedicated FEC chip” — it says the GPU is the baseband processor. This is the crux of the industry debate (see Section 4): inline acceleration ties the software more tightly to NVIDIA’s silicon roadmap, versus a look-aside/hybrid approach that preserves vendor flexibility.

The economic argument: TCO, not just performance

NVIDIA’s framing has evolved over the year. The original pitch bundled RAN compute with general AI inferencing to justify GPU economics at the cell site — the argument being that if a GPU is needed for AI anyway, it might as well also handle RAN. That drew skepticism because most cell sites don’t have latent AI demand today. The ARC-Pro reframing is narrower and more defensible: the total-cost-of-ownership case is now built on RAN compute alone, with GPU-based sites able to absorb 6G-era workloads (massive MIMO, integrated sensing and communication) via software upgrade rather than hardware replacement — and to monetize idle GPU cycles for edge AI inferencing as an upside option, not the base case.

3. How Nokia Plays It — Strategic Logic

CEO Justin Hotard (previously of Intel, hired 2025) has framed the deal as a deliberate “shift from proprietary to general-purpose hardware.” That’s a direct repudiation of Nokia’s prior approach, which leaned on Marvell-designed custom RAN silicon after moving away from Intel. The logic breaks down as follows:

• R&D leverage. Nokia’s mobile-networks R&D budget (roughly €2.1B, ~$2.4B) is about half of Ericsson’s (SEK48.9B, ~$5.2B). Nokia cannot out-design Ericsson on custom silicon dollar-for-dollar. Riding NVIDIA’s silicon roadmap converts a fixed R&D disadvantage into a variable-cost partnership.

• Narrative repositioning. Nokia has been reorganized into Network Infrastructure and Mobile Infrastructure segments explicitly to align with AI-driven capex flows from both telcos and hyperscalers/cloud providers — echoing Nokia’s parallel AWS, Google Cloud, and Databricks collaborations and its Infinera-driven push into optical/data-center interconnect.

• Hardware abstraction hedge. Nokia’s CTO has publicly stated the company built a hardware abstraction layer so RAN software runs across Marvell silicon, x86 servers, or GPUs — a hedge against being fully captive to NVIDIA even as the flagship product line goes GPU-native.

• Financial results so far are still legacy-driven. Q2 2026: 9% constant-currency net sales growth, AI & Cloud sales up 105% year-over-year to €446M, €2.8B AI/cloud order intake, gross margin improved to 46%, but free cash flow was negative €732M amid €800M of restructuring costs and supply constraints. Management guidance points to a first commercial AI-RAN platform with late-2026 pilots, 2027 commercial availability, and “meaningful” revenue not until 2028 or later — meaning the market is pricing a 2028+ revenue ramp today.

AI-RAN cumulative market opportunity through 2030 (Omdia estimate, illustrative build)

4. Who Else Gets Impacted

The most important second-order read is that NVIDIA’s push is polarizing the RAN vendor field, and it is reshaping the custom-silicon supply chain that has quietly sat behind Nokia and Samsung for years.

Ericsson (ERIC) — the strategic dissenter

Ericsson has explicitly declined the inline-GPU path. It evaluated NVIDIA’s Grace CPU during 2025 trials but chose to stay on custom ASICs (internally designed plus an Intel partnership) for its production RAN footprint, with Intel Xeon as its sole commercially supported cloud-RAN silicon partner — AMD, Arm, and NVIDIA remain “prototype support” only. CEO Börje Ekholm has called it too early to pick a silicon winner and has emphasized flexibility to run RAN software on “any architecture.” Ericsson is nonetheless rolling out its own AI-RAN features (spectral efficiency, throughput optimization) on custom silicon, arguing a power-efficient, purpose-built ASIC beats a general-purpose GPU on pure RAN workloads today. The risk for Ericsson: if 6G-era massive MIMO genuinely requires GPU-class flexibility at the radio unit — not just the baseband unit — its ASIC bet ages poorly; its own materials concede GPUs could become “essential” for advanced radio units.

Marvell (MRVL) — squeezed from two directions

Marvell has been Nokia’s primary Layer-1 custom-silicon supplier and also supplies Samsung’s RAN silicon. Nokia’s GPU pivot directly cannibalizes Marvell’s multi-year RAN ASIC roadmap with its largest customer, and Marvell has acknowledged the economics of designing custom silicon for a single RAN vendor are increasingly unviable, with Samsung’s baseband chip program reportedly looking uneconomical too. The offsetting factor: NVIDIA separately invested roughly $2B into Marvell tied to AI data-center connectivity — meaning Marvell is simultaneously losing RAN-ASIC share to NVIDIA while gaining NVIDIA-linked data-center interconnect revenue (via its XConn acquisition). Net exposure is a mix shift, not a simple headwind.

Intel (INTC) — displaced incumbent, hedged position

Intel Xeon has been the default silicon for cloud-RAN control-plane and, via Ericsson, for commercial vRAN deployments broadly. NVIDIA’s Grace CPU is a direct architectural substitute in the Nokia stack. Intel had reportedly been exploring a divestment of its network/edge group serving this market before NVIDIA and SoftBank’s combined roughly $7B investment in Intel shelved those plans — an odd twist in which NVIDIA is simultaneously displacing Intel silicon in RAN while propping up Intel’s balance sheet elsewhere.

Samsung Networks — collateral exposure

Samsung’s RAN silicon roadmap has leaned on Marvell in a manner similar to Nokia’s prior approach; as Marvell’s custom-RAN economics deteriorate industry-wide, Samsung inherits the same make-versus-buy silicon dilemma without, so far, an NVIDIA relationship of its own to offset it.

Dell (DELL) — quiet beneficiary

Dell PowerEdge servers are the reference chassis for the Nokia/NVIDIA stack — a direct, low-controversy revenue tailwind as deployments scale, analogous to Dell’s AI-server exposure elsewhere in the NVIDIA ecosystem.

Huawei / ZTE — indirectly advantaged

Not addressed directly in company disclosures, but structurally relevant: Huawei’s vertically integrated custom-silicon RAN stack continues to compete on cost and performance in non-Western markets regardless of how the NVIDIA/Nokia/Ericsson silicon debate resolves — the fight described here is largely a Western-market phenomenon.

Competitive positioning summary

5. Key Risks

• TCO remains unproven at scale. Field validation is only just beginning (T-Mobile trials 2026); the “2x spectral efficiency by 2028” claim is a vendor projection, not an operator-audited result.

• 6G timeline risk. Standardization isn’t expected to conclude until roughly 2029, with limited commercial deployment realistically starting 2030. Nokia’s GPU bet is front-loading capex and strategic commitment years ahead of the demand curve.

• Vendor lock-in optics. Nokia’s own hardware-abstraction-layer messaging is in some tension with a flagship product line that runs L1 inline on NVIDIA silicon with no separate accelerator — critics frame this as trading one form of lock-in (custom ASIC) for another (NVIDIA CUDA/GPU dependency).

• Valuation has already moved. NOK is up sharply from pre-deal levels (52-week range $4.08–$17.45) on a revenue ramp that management itself says is 2028+. Sell-side commentary has flagged the initial 40% two-day rally as “excessive” given unclear medium-term revenue potential.

• Geopolitical framing. NVIDIA has described the deal partly in terms of reshoring RAN production and leadership to the U.S. — a rationale that adds political tailwind but is not itself a commercial moat.

6. Bottom Line

For Nokia:

this is a legitimate, well-funded strategic pivot that buys relevance in the 6G narrative and diversifies away from low-margin legacy RAN hardware — but it is a multi-year, execution-dependent bet, not a near-term earnings catalyst. Current guidance puts meaningful AI-RAN revenue in 2028 at the earliest, while free cash flow remains negative through the restructuring period. Treat NOK’s move as an option on GPU-RAN winning the architecture debate, not as a re-rating already earned by fundamentals.

For the silicon supply chain:

Marvell and Intel are the names most directly disintermediated by the Nokia deal specifically, though both have partially offsetting NVIDIA-linked exposure elsewhere (Marvell’s data-center interconnect, Intel’s equity infusion). Ericsson is the explicit hedge against the thesis — if custom silicon keeps winning on TCO through the 5G-Advanced to 6G transition, Nokia’s GPU-native bet looks premature; if GPU flexibility wins, Ericsson’s silicon-diversity stance may itself become a liability.

1. RTL Synthesis

For RTL synthesis, Synopsys Design Compiler (and more recently Fusion Compiler) has been my go-to choice. Over the years, it has consistently delivered solid QoR (performance, power, area) and integrates well with signoff flows. Cadence Genus is a strong competitor and has closed the gap considerably in recent years, but in my experience Synopsys still holds a slight edge in terms of consistency and ecosystem maturity.

2. Place & Route

When it comes to digital implementation, Cadence Innovus is the tool I’ve seen deliver better PPA results in many complex designs. Innovus handles large blocks efficiently and often achieves tighter timing closure. Synopsys ICC2 and Fusion Compiler are powerful and very well integrated into Synopsys’ flow, but if I had to choose based on implementation QoR, Cadence Innovus usually comes out on top.

3. Static Timing Analysis / Signoff

For timing signoff, Synopsys PrimeTime remains the industry standard. I’ve used it for virtually every tapeout, and its accuracy and trust factor are unmatched. Cadence Tempus is a capable challenger, and I’ve seen it perform well in terms of runtime and scaling, but PrimeTime still carries the signoff authority that most foundries and customers rely on.

4. Analog / Custom IC Design

In the analog and mixed-signal space, Cadence Virtuoso has been the undisputed leader. Whenever I’ve worked with precision analog or RF designs, Virtuoso was the tool of choice. Its layout environment, PDK support, and Spectre simulator make it the default in most analog teams. Synopsys Custom Designer (and HSPICE) is competent, but I’ve rarely seen it replace Virtuoso in real analog projects.

5. High-Level Synthesis (HLS)

For HLS, I have found Cadence Stratus to be the more mature solution. While Synopsys has offered HLS options, Cadence Stratus tends to be favored in production flows I’ve observed. It handles SystemC designs well and has good integration with downstream implementation tools. Synopsys’ solutions are improving, but in practice Stratus has the stronger track record.

6. Formal Verification

In formal verification, the choice depends on the use case. For equivalence checking between RTL and gate-level, Synopsys Formality is my trusted tool—it integrates seamlessly into synthesis flows and is highly reliable. However, for property checking and broader formal verification tasks, Cadence JasperGold offers greater depth and flexibility. If I had to pick one overall, JasperGold provides broader capability, but Formality remains indispensable for equivalence signoff.

Conclusion

Both Synopsys and Cadence offer world-class tools, and the best choice often depends on the specific design challenge and the existing tool flow in place. Over the years, my pattern has been to rely on Synopsys for synthesis, timing, and equivalence checking, and on Cadence for place-and-route, analog, and formal verification depth. No single vendor wins across the board, but understanding where each shines helps build the most effective design flow.

In the fiercely competitive landscape of semiconductor manufacturing, the adoption of cutting-edge technologies often dictates leadership and profitability. Extreme Ultraviolet (EUV) lithography stands as a pivotal innovation, enabling the production of increasingly smaller and more powerful integrated circuits. However, the path to integrating such advanced technologycomes with significant challenges, including immense R&D cost and technical complexities. A recent article from Korea’s Chosun Daily, delves into Micron Technology’s seemingly cautious approach to EUV implementation in DRAM production, raising pertinent questions about its implications for the future of memory technology. While some might perceive Micron’s strategy as lagging, a closer examination reveals a calculated and potentially advantageous decision, especially when contrasted with the experiences of its key competitors.

Unlike traditional optical lithography that uses deep ultraviolet (DUV) light, EUV employs light with an extremely short wavelength of 13.5 nanometers. This allows for the creation of much finer patterns on silicon wafers, crucial for manufacturing the next generation of high-density memory chips and logic processors. The technology, primarily spearheaded by Dutch company ASML, involves complex systems that generate EUV light using tin plasma, which then reflects off a series of highly polished mirrors to project circuit patterns onto a photoresist-coated wafer. The precision and control required for this process are extraordinary, making EUV tools incredibly expensive, with a single machine costing upwards of $100 million

Micron’s stance on EUV adoption has been notably conservative. The company has opted to delay the widespread integration of EUV into its DRAM manufacturing until its 1-gamma process node, which is currently in mass production. A Micron spokesperson articulated this strategy, stating, EUV technology still lacks full stability, so we have applied it only where absolutely necessary. We believe this was the right timing after evaluating cost and productivity. This statement underscores a pragmatic approach, prioritizing stability, cost-effectiveness, and proven productivity over being the first to market with a new technology. This is a significant departure from the industry trend where being an early adopter is often seen as a competitive advantage.

In contrast, Samsung, a historical leader in the memory market, has been an aggressive early adopter of EUV technology for DRAM production. Samsung possesses a substantial fleet of over 30 EUV machines, reportedly the largest among memory manufacturers. Their early adoption was facilitated by their unique position as both a foundry and a DRAM producer, allowing them to amortize the exorbitant cost of EUV tools across both business segments. This meant that the DRAM division bore only a fraction of the total cost of each EUV machine, making early investment more financially viable for them. However, the Chosun Daily article highlights that Samsung has faced considerable challenges, stating, Samsung, which owns more than 30 EUV machines: ”the most among the three memory makers” is making adjustments to its EUV process after setbacks in its fourth- and fifth-generation 10-nanometer DRAM. This revelation suggests that despite their early and extensive investment, Samsung has encountered significant hurdles in optimizing their EUV-based DRAM production, leading to yield issues and necessitating process adjustments.

This comparison between Micron and Samsung’s experiences provides a compelling argument for Micron’s delayed EUV strategy. While Samsung’s pioneering efforts positioned them as a leader in EUV integration, their struggles with yield and process stability indicate the inherent risks associated with being at the bleeding edge of a nascent technology. Micron, by waiting, has potentially allowed the technology to mature, enabling them to bypass some of the initial pitfalls and costly adjustments that early adopters like Samsung have had to endure. This strategy of patience and observation has historically served Micron well, particularly during previous major lithography advancements, such as the introduction of immersion EUV tools.

Furthermore, the article reveals a critical detail regarding the generational lead in DRAM technology. The challenges faced by Samsung are specifically noted in their fourth- and fifth-generation 10-nanometer DRAM. Conversely, the discussion surrounding Micron’s EUV integration pertains to their sixth-generation DRAM, which was introduced in February. This indicates that Micron is, in fact, ahead of its competition in shipping a more advanced generation of DRAM. This generational lead, achieved without the widespread early adoption of EUV, further validates Micron’s strategic decision. It suggests that their existing manufacturing processes, combined with selective and targeted EUV application, have been sufficient to maintain a competitive edge and even surpass rivals in terms of product generation.

The financial implications of EUV adoption are immense. The cost of a single EUV machine is a significant capital expenditure, and the operational costs associated with maintaining and running these machines are also substantial. By delaying full-scale EUV integration, Micron has potentially saved billions in early investment and avoided the depreciation of rapidly evolving, early-generation EUV equipment. This capital can instead be allocated to other areas of research and development, or to optimizing existing, more stable manufacturing processes. Moreover, the learning curve associated with new technologies is steep. Early adopters often bear the brunt of this learning curve, investing heavily in R&D to resolve unforeseen technical issues and optimize processes. Micron’s delayed approach allows them to learn from the experiences of others, adopting a more refined and stable EUV technology when it becomes more mature and cost-effective.

Another factor to consider is the yield. In semiconductor manufacturing, yield refers to the percentage of functional chips produced from a wafer. Low yields can significantly impact profitability, especially for high-volume products like DRAM. If early EUV processes lead to lower yields due to instability or unforeseen manufacturing defects, the financial losses can be substantial. Samsung’s reported setbacks in their EUV process suggest that they have indeed grappled with yield challenges. Micron’s cautious approach, therefore, aims to ensure higher yields from the outset by implementing EUV only when its stability and productivity are well-established. This focus on yield optimization aligns with a strategy of sustainable profitability rather than aggressive, potentially risky, technological pioneering.

In conclusion, while the initial perception might be that Micron is trailing in the race for EUV adoption in DRAM manufacturing, a deeper analysis of the available information suggests a well-reasoned and potentially superior strategy. By prioritizing stability, cost-effectiveness, and learning from the early experiences of competitors like Samsung, Micron appears to be positioning itself for long-term success. Their ability to ship a more advanced generation of DRAM while maintaining a conservative EUV strategy further reinforces the validity of their approach. In the high-stakes world of semiconductor manufacturing, sometimes patience, coupled with strategic timing, can indeed be a more profitable and sustainable path than being the first to embrace every new technological frontier.

In the fiercely competitive landscape of semiconductor manufacturing, the adoption of cutting-edge technologies often dictates leadership and profitability. Extreme Ultraviolet (EUV) lithography stands as a pivotal innovation, enabling the production of increasingly smaller and more powerful integrated circuits. However, the path to integrating such advanced technologycomes with significant challenges, including immense R&D cost and technical complexities. A recent article from Korea’s Chosun Daily, brought to light by The Memory Guy, delves into Micron Technology’s seemingly cautious approach to EUV implementation in DRAM production, raising pertinent questions about its implications for the future of memory technology. While some might perceive Micron’s strategy as lagging, a closer examination reveals a calculated and potentially advantageous decision, especially when contrasted with the experiences of its key competitors.

Unlike traditional optical lithography that uses deep ultraviolet (DUV) light, EUV employs light with an extremely short wavelength of 13.5 nanometers. This allows for the creation of much finer patterns on silicon wafers, crucial for manufacturing the next generation of high-density memory chips and logic processors. The technology, primarily spearheaded by Dutch company ASML, involves complex systems that generate EUV light using tin plasma, which then reflects off a series of highly polished mirrors to project circuit patterns onto a photoresist-coated wafer. The precision and control required for this process are extraordinary, making EUV tools incredibly expensive, with a single machine costing upwards of $100 million

Micron’s stance on EUV adoption has been notably conservative. The company has opted to delay the widespread integration of EUV into its DRAM manufacturing until its 1-gamma process node, which is currently in mass production. A Micron spokesperson articulated this strategy, stating, EUV technology still lacks full stability, so we have applied it only where absolutely necessary. We believe this was the right timing after evaluating cost and productivity. This statement underscores a pragmatic approach, prioritizing stability, cost-effectiveness, and proven productivity over being the first to market with a new technology. This is a significant departure from the industry trend where being an early adopter is often seen as a competitive advantage.

In stark contrast, Samsung, a dominant force in the memory market, has been an aggressive early adopter of EUV technology for DRAM production. Samsung possesses a substantial fleet of over 30 EUV machines, reportedly the largest among memory manufacturers. Their early adoption was facilitated by their unique position as both a foundry and a DRAM producer, allowing them to amortize the exorbitant cost of EUV tools across both business segments. This meant that the DRAM division bore only a fraction of the total cost of each EUV machine, making early investment more financially viable for them. However, the Chosun Daily article highlights that Samsung has faced considerable challenges, stating, Samsung, which owns more than 30 EUV machines: ”the most among the three memory makers” is making adjustments to its EUV process after setbacks in its fourth- and fifth-generation 10-nanometer DRAM. This revelation suggests that despite their early and extensive investment, Samsung has encountered significant hurdles in optimizing their EUV-based DRAM production, leading to yield issues and necessitating process adjustments.

This comparison between Micron and Samsung’s experiences provides a compelling argument for Micron’s delayed EUV strategy. While Samsung’s pioneering efforts positioned them as a leader in EUV integration, their struggles with yield and process stability indicate the inherent risks associated with being at the bleeding edge of a nascent technology. Micron, by waiting, has potentially allowed the technology to mature, enabling them to bypass some of the initial pitfalls and costly adjustments that early adopters like Samsung have had to endure. This strategy of patience and observation has historically served Micron well, particularly during previous major lithography advancements, such as the introduction of immersion EUV tools.

Furthermore, the article subtly reveals a critical detail regarding the generational lead in DRAM technology. The challenges faced by Samsung are specifically noted in their fourth- and fifth-generation 10-nanometer DRAM. Conversely, the discussion surrounding Micron’s EUV integration pertains to their sixth-generation DRAM, which was introduced in February. This indicates that Micron is, in fact, ahead of its competition in shipping a more advanced generation of DRAM. This generational lead, achieved without the widespread early adoption of EUV, further validates Micron’s strategic decision. It suggests that their existing manufacturing processes, combined with selective and targeted EUV application, have been sufficient to maintain a competitive edge and even surpass rivals in terms of product generation.

The financial implications of EUV adoption are immense. The cost of a single EUV machine is a significant capital expenditure, and the operational costs associated with maintaining and running these machines are also substantial. By delaying full-scale EUV integration, Micron has potentially saved billions in early investment and avoided the depreciation of rapidly evolving, early-generation EUV equipment. This capital can instead be allocated to other areas of research and development, or to optimizing existing, more stable manufacturing processes. Moreover, the learning curve associated with new technologies is steep. Early adopters often bear the brunt of this learning curve, investing heavily in R&D to resolve unforeseen technical issues and optimize processes. Micron’s delayed approach allows them to learn from the experiences of others, adopting a more refined and stable EUV technology when it becomes more mature and cost-effective.

Another factor to consider is the yield. In semiconductor manufacturing, yield refers to the percentage of functional chips produced from a wafer. Low yields can significantly impact profitability, especially for high-volume products like DRAM. If early EUV processes lead to lower yields due to instability or unforeseen manufacturing defects, the financial losses can be substantial. Samsung’s reported setbacks in their EUV process suggest that they have indeed grappled with yield challenges. Micron’s cautious approach, therefore, aims to ensure higher yields from the outset by implementing EUV only when its stability and productivity are well-established. This focus on yield optimization aligns with a strategy of sustainable profitability rather than aggressive, potentially risky, technological pioneering.

In conclusion, while the initial perception might be that Micron is trailing in the race for EUV adoption in DRAM manufacturing, a deeper analysis of the available information suggests a well-reasoned and potentially superior strategy. By prioritizing stability, cost-effectiveness, and learning from the early experiences of competitors like Samsung, Micron appears to be positioning itself for long-term success. Their ability to ship a more advanced generation of DRAM while maintaining a conservative EUV strategy further reinforces the validity of their approach. In the high-stakes world of semiconductor manufacturing, sometimes patience, coupled with strategic timing, can indeed be a more profitable and sustainable path than being the first to embrace every new technological frontier.

A New Dawn for European Tech

Europe's technology ecosystem is at a pivotal juncture, poised for unprecedented growth and global leadership. A recent report by McKinsey and Boardwave, titled "Europe's Moonshot Moment: Fueling its Tech Ecosystem for Scale," highlights the significant strides made by European tech companies over the past decade and outlines a strategic roadmap to overcome persistent challenges and unlock the continent's full potential. This comprehensive analysis, based on extensive research and insights from over 30 European tech founders, CEOs, investors, and ecosystem leaders, underscores the critical need for coordinated action across four key levers: Leadership, Incentives, Focus, and Teaming (LIFT).Over the last ten years, the European software startup landscape has witnessed a remarkable fivefold increase in the number of companies, attracting over $425 billion in venture funding—a tenfold increase compared to the preceding decade. Today, Europe boasts more than 280 software companies generating over €100 million in annual recurring revenue (ARR). Among these, approximately one-fifth are either 'emergent leaders' (achieving over €100 million ARR within ten years) or 'super performers' (exceeding €500 million ARR within 20 years). These figures, as illustrated in Exhibit 1 of the report, demonstrate a vibrant and rapidly maturing ecosystem.

Exhibit 1: Europe’s tech ecosystem has gained meaningful momentum in the past decade.

These successful companies are not merely isolated triumphs; they are actively fostering a new generation of entrepreneurs. Much like PayPal's role in spawning companies such as LinkedIn, Yelp, and YouTube, Europe's tech champions are now fueling their own innovation pipelines. Notable examples include Klarna, Revolut, Spotify, and Zalando, which have collectively generated over 215 spin-offs. Furthermore, the emergence of innovation clusters across Europe, bringing together founders, investors, universities, and tech talent, signifies a growing collaborative environment conducive to technological competitiveness. Exhibit 2 visually represents Europe's strong position in the global emerging ecosystem landscape.

Exhibit 2: Europe is home to nearly half of the top 100 emerging ecosystems.

Despite this impressive momentum, the report identifies a critical hurdle: Europe's innovation engine often stalls before achieving true global scale. Fewer companies are founded in Europe compared to the United States, and those that do emerge tend to scale at a slower pace. European software startups, on average, take 15 years to reach €100 million in ARR, five years longer than their US counterparts. The disparity in growth thresholds becomes even more pronounced at higher revenue levels (€10 million, €30 million, and €100 million ARR). This scaling challenge is further highlighted by the fact that a significantly smaller percentage of European firms reaching €100 million ARR subsequently scale to €1 billion compared to their US peers. Exhibit 3 provides a detailed comparison of European and US software companies, emphasizing these growth disparities.

This gap in scaling potential has substantial economic implications, with estimates suggesting that €500 billion to €1 trillion in annual value could be at stake for Europe by 2030. However, the report asserts that a unique confluence of factors—new technology arenas, evolving geopolitics, and a changing operating environment—presents a rare opportunity for Europe to reset its innovation trajectory and close the gap with global leaders like the United States and China. The report delves into these forces and proposes actionable strategies for various ecosystem players to seize this moonshot moment and propel Europe's tech sector to global prominence.

The LIFT Framework: A Coordinated Approach to Scale

To effectively seize this "moonshot moment," the McKinsey report proposes a four-pronged framework, encapsulated by the acronym LIFT: Leadership, Incentives, Focus, and Teaming. These interconnected levers provide a comprehensive strategy for various ecosystem players—including founders, CEOs, institutions, investors, and industry groups—to collectively drive Europe's tech sector towards sustained global scale.

Leadership: Cultivating a Culture of Boldness and Growth

At the heart of Europe's tech transformation lies the imperative to foster a leadership culture that prioritizes scale and long-term growth. For founders and CEOs, this translates into building diverse, growth-oriented management teams and boards of directors. The report emphasizes the importance of embedding a risk-taking mindset within company culture, moving beyond the traditional European aversion to failure. This shift is crucial for encouraging ambitious ventures and disruptive innovation. For institutions, investors, and other ecosystem players, the role of leadership involves providing strategic guidance for scaling. This includes developing and disseminating playbooks that codify best practices for growth, offering mentorship, and actively supporting pan-European innovation initiatives. By creating a supportive environment that champions bold leadership, Europe can nurture the next generation of tech giants.

Incentives: Aligning Financial Structures for Long-Term Innovation

The report highlights the need to align financial structures with the goal of rewarding long-term, innovation-driven growth. This involves a re-evaluation of existing incentive models to encourage ambition over short-term gains. For companies, this means adopting founder-friendly equity models that provide founders with sufficient ownership and control to pursue long-term visions. It also necessitates access to patient, long-term capital that can sustain growth through various stages of development, rather than solely focusing on early-stage investments. Beyond individual companies, the report suggests that targeted university incentives can play a vital role in fostering entrepreneurial talent and research commercialization. Furthermore, growth-oriented procurement policies by governments and corporations can create significant market opportunities for innovative startups. Finally, consistent fiscal policies across European markets are essential to reduce complexity and provide a stable environment for tech companies to thrive and expand across borders.

Focus: Directing Resources Towards Global Scale

Effective resource allocation is paramount for achieving global scale. The report advocates for a strategic focus on areas that will genuinely drive scale, rather than merely localized growth. This begins with globally-minded founders who design their businesses for international expansion from the outset. This involves building products and services with global applicability and developing go-to-market strategies that transcend national borders. Strategic partnerships and targeted mergers and acquisitions (M&A) are identified as key avenues for accelerating expansion and gaining market share. Ecosystem players have a crucial role in shaping this environment by actively supporting critical technology sectors, such as AI, quantum computing, and advanced connectivity. Equally important is the streamlining of foundational enablers of scale, including talent mobility across European countries, administrative simplicity to reduce bureaucratic hurdles, and cross-border alignment of regulations and standards. The report notes that advancements like generative AI, with its capabilities for real-time translation and automated compliance, can significantly empower smaller teams to scale more efficiently across traditional barriers, offering immense operating leverage.

Teaming: Fostering Collaboration and Inspiring Future Generations

Teaming, the fourth lever, emphasizes the importance of collaborative learning and inspiring the next generation of tech leaders. This involves the execution of well-defined go-to-market (GTM) strategies, supported by skilled talent capable of driving international expansion. Engagement with industry groups and networks is crucial for sharing lessons learned, disseminating best practices, and accelerating collective progress across the ecosystem. The report stresses the need to cultivate forums and initiatives where ideas, experiences, and scaling successes are openly exchanged. This fosters a culture where entrepreneurship is celebrated, and aspiring founders are inspired by the achievements of their predecessors. By building strong networks and promoting knowledge sharing, Europe can create a virtuous cycle of innovation and growth.

Overcoming Persistent Challenges and Seizing New Opportunities

While Europe's tech ecosystem has demonstrated significant progress, the McKinsey report candidly addresses the persistent structural barriers that have historically constrained its ability to produce global champions. These include fragmented markets, conservative corporate norms that can hinder risk-taking, and a slower flow of late-stage capital compared to early-stage investment. However, the report argues that a rare alignment of geopolitical, regulatory, and technological shifts is now creating unprecedented momentum and a unique window of opportunity for Europe to overcome these challenges and build global leadership.New technology arenas, particularly in areas like Artificial Intelligence (AI) and automation, are opening up significant leadership opportunities. European players such as ElevenLabs, Mistral AI, and Wayve are already emerging as major global contenders in these fields. This momentum is particularly critical as it mirrors the early internet and cloud eras, where initial advances were converted into lasting global dominance by US players. The report suggests that Europe has a chance to learn from past experiences and convert its current technological advancements into sustained leadership.In parallel, geopolitical shifts are prompting governments to reassess technological sovereignty. This has led to new regulations and increased investment in domestic technology ecosystems, pushing corporations to prioritize local suppliers. This trend can create a more favorable environment for European tech companies to grow and compete. Furthermore, long-standing barriers to innovation, such as Europe's fragmented landscape, are being softened by technological advancements and policy reforms. The adoption of consumption-based software models and cloud technology, for instance, has lowered the cost and complexity of new technology adoption for enterprises, thereby expanding market opportunities for startups. Recent tax and data sovereignty reforms are also expected to provide European tech companies with greater access to continental markets that were previously dominated by US tech giants. Discussions around implementing a "28th regime" alongside existing national frameworks further promise to reshape the startup landscape, fostering a more unified and conducive environment for growth.

Conclusion: A Collective Effort for a Brighter Future

Europe's tech ecosystem stands at a critical inflection point. The McKinsey report, "Europe's Moonshot Moment: Fueling its Tech Ecosystem for Scale," provides a compelling narrative of progress, persistent challenges, and a clear path forward. The LIFT framework—Leadership, Incentives, Focus, and Teaming—offers a actionable blueprint for all stakeholders to collaborate and drive the continent's tech sector to new heights. By embracing a culture of boldness, aligning financial incentives with long-term growth, strategically focusing resources on global scale, and fostering a collaborative environment, Europe can indeed seize this moonshot moment. The report concludes with a powerful sentiment from a European founder: "It’s not about breaking the US moat—it’s about building our own alongside it." This encapsulates the ambition and the collaborative spirit required to position Europe as a formidable force in the global technology landscape, realizing its full economic potential and shaping the future of innovation.

A New Dawn for European Tech

Europe's technology ecosystem is at a pivotal juncture, poised for unprecedented growth and global leadership. A recent report by McKinsey and Boardwave, titled "Europe's Moonshot Moment: Fueling its Tech Ecosystem for Scale," highlights the significant strides made by European tech companies over the past decade and outlines a strategic roadmap to overcome persistent challenges and unlock the continent's full potential. This comprehensive analysis, based on extensive research and insights from over 30 European tech founders, CEOs, investors, and ecosystem leaders, underscores the critical need for coordinated action across four key levers: Leadership, Incentives, Focus, and Teaming (LIFT).Over the last ten years, the European software startup landscape has witnessed a remarkable fivefold increase in the number of companies, attracting over $425 billion in venture funding—a tenfold increase compared to the preceding decade. Today, Europe boasts more than 280 software companies generating over €100 million in annual recurring revenue (ARR). Among these, approximately one-fifth are either 'emergent leaders' (achieving over €100 million ARR within ten years) or 'super performers' (exceeding €500 million ARR within 20 years). These figures, as illustrated in Exhibit 1 of the report, demonstrate a vibrant and rapidly maturing ecosystem.

Exhibit 1: Europe’s tech ecosystem has gained meaningful momentum in the past decade.

These successful companies are not merely isolated triumphs; they are actively fostering a new generation of entrepreneurs. Much like PayPal's role in spawning companies such as LinkedIn, Yelp, and YouTube, Europe's tech champions are now fueling their own innovation pipelines. Notable examples include Klarna, Revolut, Spotify, and Zalando, which have collectively generated over 215 spin-offs. Furthermore, the emergence of innovation clusters across Europe, bringing together founders, investors, universities, and tech talent, signifies a growing collaborative environment conducive to technological competitiveness. Exhibit 2 visually represents Europe's strong position in the global emerging ecosystem landscape.

Exhibit 2: Europe is home to nearly half of the top 100 emerging ecosystems.

Despite this impressive momentum, the report identifies a critical hurdle: Europe's innovation engine often stalls before achieving true global scale. Fewer companies are founded in Europe compared to the United States, and those that do emerge tend to scale at a slower pace. European software startups, on average, take 15 years to reach €100 million in ARR, five years longer than their US counterparts. The disparity in growth thresholds becomes even more pronounced at higher revenue levels (€10 million, €30 million, and €100 million ARR). This scaling challenge is further highlighted by the fact that a significantly smaller percentage of European firms reaching €100 million ARR subsequently scale to €1 billion compared to their US peers. Exhibit 3 provides a detailed comparison of European and US software companies, emphasizing these growth disparities.

This gap in scaling potential has substantial economic implications, with estimates suggesting that €500 billion to €1 trillion in annual value could be at stake for Europe by 2030. However, the report asserts that a unique confluence of factors—new technology arenas, evolving geopolitics, and a changing operating environment—presents a rare opportunity for Europe to reset its innovation trajectory and close the gap with global leaders like the United States and China. The report delves into these forces and proposes actionable strategies for various ecosystem players to seize this moonshot moment and propel Europe's tech sector to global prominence.

The LIFT Framework: A Coordinated Approach to Scale

To effectively seize this "moonshot moment," the McKinsey report proposes a four-pronged framework, encapsulated by the acronym LIFT: Leadership, Incentives, Focus, and Teaming. These interconnected levers provide a comprehensive strategy for various ecosystem players—including founders, CEOs, institutions, investors, and industry groups—to collectively drive Europe's tech sector towards sustained global scale.

Leadership: Cultivating a Culture of Boldness and Growth

At the heart of Europe's tech transformation lies the imperative to foster a leadership culture that prioritizes scale and long-term growth. For founders and CEOs, this translates into building diverse, growth-oriented management teams and boards of directors. The report emphasizes the importance of embedding a risk-taking mindset within company culture, moving beyond the traditional European aversion to failure. This shift is crucial for encouraging ambitious ventures and disruptive innovation. For institutions, investors, and other ecosystem players, the role of leadership involves providing strategic guidance for scaling. This includes developing and disseminating playbooks that codify best practices for growth, offering mentorship, and actively supporting pan-European innovation initiatives. By creating a supportive environment that champions bold leadership, Europe can nurture the next generation of tech giants.

Incentives: Aligning Financial Structures for Long-Term Innovation

The report highlights the need to align financial structures with the goal of rewarding long-term, innovation-driven growth. This involves a re-evaluation of existing incentive models to encourage ambition over short-term gains. For companies, this means adopting founder-friendly equity models that provide founders with sufficient ownership and control to pursue long-term visions. It also necessitates access to patient, long-term capital that can sustain growth through various stages of development, rather than solely focusing on early-stage investments. Beyond individual companies, the report suggests that targeted university incentives can play a vital role in fostering entrepreneurial talent and research commercialization. Furthermore, growth-oriented procurement policies by governments and corporations can create significant market opportunities for innovative startups. Finally, consistent fiscal policies across European markets are essential to reduce complexity and provide a stable environment for tech companies to thrive and expand across borders.

Focus: Directing Resources Towards Global Scale

Effective resource allocation is paramount for achieving global scale. The report advocates for a strategic focus on areas that will genuinely drive scale, rather than merely localized growth. This begins with globally-minded founders who design their businesses for international expansion from the outset. This involves building products and services with global applicability and developing go-to-market strategies that transcend national borders. Strategic partnerships and targeted mergers and acquisitions (M&A) are identified as key avenues for accelerating expansion and gaining market share. Ecosystem players have a crucial role in shaping this environment by actively supporting critical technology sectors, such as AI, quantum computing, and advanced connectivity. Equally important is the streamlining of foundational enablers of scale, including talent mobility across European countries, administrative simplicity to reduce bureaucratic hurdles, and cross-border alignment of regulations and standards. The report notes that advancements like generative AI, with its capabilities for real-time translation and automated compliance, can significantly empower smaller teams to scale more efficiently across traditional barriers, offering immense operating leverage.

Teaming: Fostering Collaboration and Inspiring Future Generations

Teaming, the fourth lever, emphasizes the importance of collaborative learning and inspiring the next generation of tech leaders. This involves the execution of well-defined go-to-market (GTM) strategies, supported by skilled talent capable of driving international expansion. Engagement with industry groups and networks is crucial for sharing lessons learned, disseminating best practices, and accelerating collective progress across the ecosystem. The report stresses the need to cultivate forums and initiatives where ideas, experiences, and scaling successes are openly exchanged. This fosters a culture where entrepreneurship is celebrated, and aspiring founders are inspired by the achievements of their predecessors. By building strong networks and promoting knowledge sharing, Europe can create a virtuous cycle of innovation and growth.

Overcoming Persistent Challenges and Seizing New Opportunities

While Europe's tech ecosystem has demonstrated significant progress, the McKinsey report candidly addresses the persistent structural barriers that have historically constrained its ability to produce global champions. These include fragmented markets, conservative corporate norms that can hinder risk-taking, and a slower flow of late-stage capital compared to early-stage investment. However, the report argues that a rare alignment of geopolitical, regulatory, and technological shifts is now creating unprecedented momentum and a unique window of opportunity for Europe to overcome these challenges and build global leadership.New technology arenas, particularly in areas like Artificial Intelligence (AI) and automation, are opening up significant leadership opportunities. European players such as ElevenLabs, Mistral AI, and Wayve are already emerging as major global contenders in these fields. This momentum is particularly critical as it mirrors the early internet and cloud eras, where initial advances were converted into lasting global dominance by US players. The report suggests that Europe has a chance to learn from past experiences and convert its current technological advancements into sustained leadership.In parallel, geopolitical shifts are prompting governments to reassess technological sovereignty. This has led to new regulations and increased investment in domestic technology ecosystems, pushing corporations to prioritize local suppliers. This trend can create a more favorable environment for European tech companies to grow and compete. Furthermore, long-standing barriers to innovation, such as Europe's fragmented landscape, are being softened by technological advancements and policy reforms. The adoption of consumption-based software models and cloud technology, for instance, has lowered the cost and complexity of new technology adoption for enterprises, thereby expanding market opportunities for startups. Recent tax and data sovereignty reforms are also expected to provide European tech companies with greater access to continental markets that were previously dominated by US tech giants. Discussions around implementing a "28th regime" alongside existing national frameworks further promise to reshape the startup landscape, fostering a more unified and conducive environment for growth.

Conclusion: A Collective Effort for a Brighter Future

Europe's tech ecosystem stands at a critical inflection point. The McKinsey report, "Europe's Moonshot Moment: Fueling its Tech Ecosystem for Scale," provides a compelling narrative of progress, persistent challenges, and a clear path forward. The LIFT framework—Leadership, Incentives, Focus, and Teaming—offers a actionable blueprint for all stakeholders to collaborate and drive the continent's tech sector to new heights. By embracing a culture of boldness, aligning financial incentives with long-term growth, strategically focusing resources on global scale, and fostering a collaborative environment, Europe can indeed seize this moonshot moment. The report concludes with a powerful sentiment from a European founder: "It’s not about breaking the US moat—it’s about building our own alongside it." This encapsulates the ambition and the collaborative spirit required to position Europe as a formidable force in the global technology landscape, realizing its full economic potential and shaping the future of innovation.

Technical Innovations in High NA EUV

ASML's High NA EUV platform, called "EXE," incorporates several groundbreaking technical innovations:

Anamorphic Optics: Rather than uniformly shrinking patterns, High NA systems use an ingenious anamorphic design that demagnifies patterns by 4x in one direction and 8x in the other. This approach solves reflection issues that would otherwise occur with larger mirrors while allowing chipmakers to continue using traditionally sized reticles.

Faster Wafer and Reticle Stages: To compensate for the smaller exposure field size, High NA systems incorporate significantly faster stages. The wafer stage accelerates at 8g (twice as fast as previous systems), while the reticle stage achieves an astonishing 32g acceleration—equivalent to a race car going from 0 to 100 km/h in just 0.09 seconds.

Enhanced Source Power and Reliability: The first High NA systems have demonstrated source power at 110% of target—the first time a new EUV system has exceeded its initial target. Reliability has reached 85%, significantly better than previous systems at comparable development stages.4.Improved Overlay Performance: High NA systems achieve overlay performance of 0.6nm when aligned with standard EUV tools, enabling chipmakers to mix and match toolsets with excellent results.

When: Adoption Timeline for High NA EUV

Current Deployment Status

The journey from concept to commercial reality for High NA EUV has been long but is now bearing fruit. After nearly a decade of research and development, ASML shipped the first modules of its TWINSCAN EXE:5000 High NA EUV system to Intel in December 2023. This milestone marked the beginning of the commercial deployment phase for this groundbreaking technology. As of mid-2025, only five High NA EUV systems have been shipped worldwide. Intel has been the most aggressive early adopter, having received and installed two systems at its Fab D1X in Hillsboro, Oregon. The company has already exposed approximately 30,000 wafers across these two systems, providing valuable early learning and characterization data.TSMC received its first High NA EUV system in Q4 2024, which is installed at its R&D center in Hsinchu, Taiwan. Samsung has also begun integrating High NA technology into its manufacturing roadmap, with early systems being ramped up for production. Also, IMEC is belgium has an EUV system at its pilot line for R&D purposes.

Node-Specific Adoption Plans

Different semiconductor manufacturers have varying strategies for High NA EUV adoption:

Intel: High NA EUV is a critical part of Intel's product strategy for its 14A node, though the company has stated that 14A is technically possible with only standard EUV. Intel views High NA as essential for maintaining process leadership beyond 18A.

TSMC: While initially appearing more cautious about High NA adoption, TSMC is now integrating the technology into its roadmap. Some reports suggest TSMC may skip High NA for its A14 process, potentially introducing it at a later node.

Samsung: Samsung has reported that High NA could reduce its manufacturing cycle time by 60%, suggesting significant efficiency improvements. The company hasn't yet announced on which node will it adopt High NA.

Memory Manufacturers: Companies like Micron and SK Hynix are also expected to adopt High NA EUV, particularly for advanced memory nodes requiring similar transistor densities as logic chips.

Cost Viability of High NA

The notion that High NA EUV could be cost-effective despite its astronomical price tag hinges on its potential to simplify patterning processes for the most complex layers. While the upfront costs are staggering, the savings come from reducing multi-patterning steps, improving yields, and accelerating cycle times. Let’s break down the math:

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Why High NA Could Be Cost-Effective: The Core Argument

1. Replaces Multi-Patterning

Current EUV struggles with ultra-dense features (e.g., <16nm pitch). To print these, chipmakers use:

- Double Patterning (LELE/SAQP): 2+ lithography/etch cycles per layer.

- Quadruple Patterning: 4+ cycles (common at 3nm/2nm nodes).

Each cycle adds masks, processing time, defects, and costs.

2. High NA’s Advantage

Higher resolution enables single-exposure patterning for layers that previously required 2–4 cycles. This eliminates redundant steps.

Cost Trade-Off Calculation: A Simplified Example

Assumptions for a critical metal layer (e.g., M0/M1) at 2nm node:

- Standard EUV (Multi-Patterning):

- Quadruple patterning = 4 masks + 4 litho/etch cycles.

- Cost per mask set: $2M (total masks: $8M).

- Process cost per wafer: $500/wafer (litho/etch steps).

- Cycle time: 15 days

- High NA EUV (Single Exposure):

- 1 mask + 1 litho/etch cycle.

- Mask cost: $3M (50% more complex).

- Process cost per wafer: $700/wafer (due to higher tool depreciation).

- Cycle time: 5 days.

Cost Comparison per 10,000 Wafers

Based on the above numbers, here is a brief comparison of costs per 10,000 wafers

Key Savings:

- Mask Costs: High NA saves $5M on masks (despite higher per-mask cost).

- Cycle Time:10-day reduction per lot → faster time-to-market for high-margin chips

- Yield: Fewer steps = fewer defects. If multi-patterning adds 0.5% defects/step, High NA could save 2% yield (worth $20M on $1,000/chip wafers).

When High NA Breaks Even: The Utilization Factor

Assuming 140wph, An EUV/DUV machines can process roughly a million wafers per year. Assuming 5 years time horizon, here's a rough cost comparison between standard EUV and High NA EUV lithography systems for processing 5 million wafers over 5 years, using current industry benchmarks.

Key Assumptions

Below is the cost comparison of High NA vs standard EUV for 5 years:

Machine Depreciation:

Operational Cost:

Yield Advantage:

Combining the above costs, we end up with the following table showing $400M cost savings with high NA EUV.

Key Insights

1. Machine Efficiency Wins

High NA's 21% higher throughput (170 vs. 140 wph) reduces machine count by 50% – 1 High NA tool replaces 2 standard EUV toolsfor this volume.

2.Yield is the Game-Changer

High NA's single-patterning reduces defects. A 1% yield gain saves 50,000 wafers – worth $750M at $15,000/wafer (typical HPC logic value).

3. Operational Costs Tradeoff

High NA has higher consumables/energy costs (+$350M), but this is dwarfed by yield savings.

4. Capex Neutrality

Despite double the price per machine, High NA's efficiency makes total tool costs identical ($430M for both).

Breakeven Thresholds

- High NA becomes cheaper if:

- Yield gain ≥ 0.53% (with $15k/wafer value)

- Annual volume ≥ 900K wafers

- Below 900K wafers/year, standard EUV is cheaper.

It has been reported that Huawei is providing full support to China's largest foundry (semiconductor contract manufacturing) SMIC for the successful mass production of the 5㎚ (nanometer, one billionth of a meter) process scheduled for operation next year. As the advanced processes of TSMC and Samsung Electronics cannot be utilized due to US regulations, it seems that Huawei is tightening the reins on cooperation such as equipment development so that SMIC, a domestic company, can stabilize the 5㎚ process.

According to industry sources on the 1st, SMIC plans to start operating the foundry 5㎚ process next year. SMIC plans to complete the mass companies, including DeepSeek, to develop AI models. The Ascend 910C is known to have been mass-produced using SMIC's 7nm process.

There is a prevailing view that Huawei's mass production of next-generation AI chips will be hindered as SMIC's advanced process is still at the 7㎚ level. Currently, Nvidia, AMD, Intel, etc. are manufacturing AI chips using TSMC's advanced process of 3㎚ or less, so in order to compete with them, it is essential to apply a fine process that can improve chip performance.

To this end, Huawei is understood to be risking its life to ensure smooth mass production of the 5㎚ process of SMIC, a domestic foundry company. Chinese semiconductor equipment company 'SiCarrier', known to be developing equipment in cooperation with Huawei, unveiled a number of equipment solutions applicable to fine processes at SEMICON China 2025 last week. The company is known to have registered a patent for a deep ultraviolet (DUV) equipment process that can replace EUV exposure equipment in the 5㎚ process . In addition, Huawei is said to be strengthening cooperation with SMIC, such as process optimization, so that it can maximize the performance of its chips.

The Hong Kong South China Morning Post (SCMP) reported that “Psycarrier registered a patent for manufacturing 5nm semiconductors using DUV equipment two years ago. This is also related to SMIC using DUV to manufacture Huawei’s application processors (AP) using a 7nm process.”

◇ SMIC 5㎚ Yield Around 30%… “Process Price Will Be 50% More Expensive Than TSMC”

The problem is that when using DUV equipment, the precision is lower than that of EUV equipment, resulting in lower yields. If DUV is used instead of EUV, there is a disadvantage in that the semiconductor photo paper position must be adjusted and light must be projected multiple times. Normally, when using EUV in the 5㎚ manufacturing process, the exposure process is repeated once, or at most twice, but when replaced with DUV, it must be repeated at least four times. As the process becomes more complicated, the yield is bound to become unstable, and the performance of the semiconductor is likely to deteriorate.

Park Yoo-ak, a researcher at Kiwoom Securities, said, “SMIC’s 5㎚ process yield is expected to be less than one-third of that,” and “Due to the low yield, the price of the 5㎚ process is also expected to be 50% more expensive than TSMC.” Currently, TSMC’s 5㎚ process yield is over 90%, while SMIC’s 5㎚ process yield is expected to be around 30%.

A semiconductor industry insider said, “The prevailing analysis is that SMIC’s 5㎚ process yield and performance will fall far short of TSMC and Samsung Electronics’ processes,” but added, “If the process stabilizes thanks to domestic semiconductor manufacturing demand and the level of Chinese semiconductor equipment companies improves, they can quickly increase their market share, which poses a threat to competitors.

TSMC’s 2nm N2 Status

TSMC’s 2nm N2 process, which represents its first major gate-all-around (GAA) transistor architecture, has achieved significant milestones. As of December 2024, trial production at the company’s Baoshan facility in Taiwan demonstrated a 60% yield rate, a critical indicator of process maturity[4]. This figure marks a substantial improvement from earlier stages: in April 2023, yields for 256 Mb SRAM test vehicles stood at 35%, rising to 70% by March 2024[1].

The N2 process has already surpassed 90% of its target performance metrics, with power efficiency and transistor density aligning with projections[1]. Key to this success is TSMC’s decision to prioritize SRAM yield optimization—a strategic move, as SRAM cells are highly sensitive to process variations and serve as reliable proxies for overall node health. The 256 Mb SRAM yield exceeding 80% in certain batches by mid-2024 provided early confidence in the node’s scalability[1].

Customer Engagement and Market Readiness

TSMC’s customer pipeline for N2 is robust, with over twice as many new tape-outs (NTOs) in the node’s first year compared to its 5nm N5 process[1]. This surge reflects strong demand from hyperscalers and AI chip designers, particularly for high-performance computing (HPC) applications. Apple and Nvidia are going to be early adopters, with the former planning to integrate N2-based chips into its iPhone 18 Pro lineup in 2026[4]. However, the node’s premium pricing—reportedly $30,000 per wafer, double the cost of 5nm—may limit initial adoption to high-margin products[4].

Mass production is scheduled to begin in late 2025 at TSMC’s Kaohsiung facility, which has undergone extensive upgrades to support GAA lithography and backside power delivery[7]. The company’s decision to conduct risk production of 5,000 wafers in Hsinchu County by January 2025 further validated the node’s readiness, with no major deviations from performance or yield targets[7].

Samsung’s 2nm SF2 Process Update

Samsung’s 2nm SF2 process, developed under its "Shell-First" (SF) initiative, has achieved a 30% yield in trial production runs as of February 2025[2][5]. While this represents a marked improvement over the company’s troubled 3nm and 4nm nodes, it remains well below the 70% threshold typically required for cost-effective mass production. The low yield stems from persistent issues in GAA transistor integration, particularly with multi-bridge channel uniformity and contact resistance variability[5].

The Exynos 2600, Samsung’s test vehicle for SF2, has demonstrated a 12% performance uplift and 25% power efficiency gain over its 3nm predecessor[2]. However, these metrics come with caveats: the improvements were measured under controlled conditions and may not fully reflect real-world variability. Moreover, Samsung’s decision to prioritize mobile applications (e.g., smartphone SoCs) over HPC designs has limited its ability to attract high-volume customers like Qualcomm and AMD, which remain skeptical of yield stability[2].

Faced with yield challenges, Samsung has pivoted resources from its struggling 3nm GAA node to accelerate SF2 development. The company’s Hwaseong fab is undergoing a $10 billion upgrade to house "S3" production lines dedicated to 2nm, with pilot runs expected to commence in Q4 2025[5]. This facility will employ advanced extreme ultraviolet (EUV) lithography tools from ASML, including the Twinscan EXE:5200, to improve overlay accuracy and reduce stochastic defects.

Samsung’s foundry roadmap aims to capture an ambitious 20% of the advanced node market by 2026, targeting automotive and IoT applications where yield tolerances are less stringent[5]. However, regaining trust from major clients remains a hurdle. The company’s 4nm yield, once struggling below 50%, now exceeds 80% after two years of optimization—a trajectory it hopes to replicate with SF2[5].

Intel’s 18A Process Status

Intel’s 18A node, positioned as a 1.8nm-class technology, has encountered severe yield issues, with early 2025 reports citing 20–30% yields for Panther Lake engineering samples[3]. These figures fall far short of the 70% threshold needed for viable mass production, casting doubt on Intel’s ability to meet its late-2025 timeline. The low yields primarily stem from complexities in integrating RibbonFET transistors and PowerVia backside power delivery—a dual transformation that no other foundry has attempted simultaneously[6].

Internal challenges compound these technical hurdles. Ming-Chi Kuo, a prominent industry analyst, notes that Intel Foundry Services (IFS) struggles with "organizational inertia" and supply chain management inefficiencies, hampering collaboration with external clients[3]. For instance, IFS’s insistence on using proprietary metrology tools, rather than industry-standard equipment from KLA and Applied Materials, has slowed defect analysis and process corrections.

Despite these setbacks, Intel maintains that 18A offers density and performance advantages over TSMC’s N2, particularly in SRAM cell scaling[6]. The company has secured commitments from the U.S. Department of Defense for legacy node production but has yet to announce major commercial clients for 18A. This contrasts sharply with TSMC’s N2, which has already garnered over 50 tape-outs, including six for AI accelerators[1][7].

Intel’s partnership with ARM to optimize 18A for mobile designs signals a strategic shift toward diversification[6]. However, the foundry’s historical focus on internal CPU production has left it with limited experience in multi-client wafer processing—a gap TSMC and Samsung bridged years ago.

Learning Curves on Leading Edge Nodes

TSMC’s yield progression from 35% to 60% over 18 months exemplifies the "learning curve advantage" inherent in its platform-based node development. By reusing 70% of N3P design rules in N2, TSMC reduced integration risks and accelerated defect root-cause analysis[1]. In contrast, Samsung’s yield improvements have been linear rather than exponential, reflecting a lack of process continuity between nodes. Intel’s 18A, as a ground-up redesign, lacks such synergies, forcing the company to confront both transistor and power delivery challenges concurrently.

At $30,000 per wafer, TSMC’s N2 commands a 100% premium over N5, reflecting the rising costs of GAA and backside power delivery[4]. Samsung’s SF2 wafers are priced 15% lower at $25,500, a discount aimed at compensating for yield-related risks[2]. Intel has not disclosed 18A pricing, but analysts estimate $35,000 per wafer based on R&D amortization—a rate that may prove prohibitive given current yields[3].

Conclusion:

The yield disparities between TSMC (60%), Samsung (30%), and Intel (20–30%) underscore the complex nature of advanced node development. TSMC’s systematic yield ramp, bolstered by deep customer collaborations and process continuity, positions it to dominate 2nm production through 2026. Samsung, while trailing, has narrowed the gap with TSMC compared to previous nodes, suggesting potential for late-cycle competitiveness. Intel’s 18A struggles, however, reveal systemic issues in balancing process innovation with foundry economics—a misalignment that may require strategic partnerships or government subsidies to resolve. May be the current leadership change can help?

Citations:

[1] TSMC: Performance and Yields of 2nm on Track, Mass Production ...

https://www.anandtech.com/show/21413/tsmc-performance-and-yields-of-2nm-on-track-mass-production-to-start-in-2025

[2] Samsung's Exynos 2600 Hits 30% Yield on 2nm Process - SemiWiki https://semiwiki.com/forum/threads/samsungs-exynos-2600-hits-30-yield-on-2nm-process-a-step-toward-closing-the-gap-with-tsmc.22100/

[3] Intel 18A process has 'disappointing' yield rates of 20-30% with ... https://www.tweaktown.com/news/103467/intel-18a-process-has-disappointing-yield-rates-of-20-30-with-mass-production-now-impossible/index.html

[4] TSMC hits 60% yield on 2nm chip trial production - GSMArena.com https://semiwiki.com/forum/threads/samsungs-exynos-2600-hits-30-yield-on-2nm-process-a-step-toward-closing-the-gap-with-tsmc.22100/

[5] Samsung Reportedly Progressing Well with 2 nm GAA Yields, Late ... https://www.techpowerup.com/333329/samsung-reportedly-progressing-well-with-2-nm-gaa-yields-late-2025-mass-production-phase-looms

[6] How 18A Fab Process Can Help Intel Stock In 2025 - Nasdaq https://www.nasdaq.com/articles/how-18a-fab-process-can-help-intel-stock-2025

[7] TSMC completes risk production of 2nm process with 5000 wafers https://technode.com/2025/01/03/tsmc-completes-risk-production-of-2nm-process-with-5000-wafers/

[8] First tests of Samsung's 2nm process look optimistic - Mezha.Media https://mezha.media/en/2025/02/10/first-tests-of-samsung-s-2nm-process-look-optimistic/

[9] Intel's 18A process: Poor yield delays mass production | igor´sLAB https://www.igorslab.de/en/intels-18a-process-poor-yield-delays-mass-production/

[10] TSMC 2 nm Wafer Output Projected to Reach ... - TechPowerUp https://www.techpowerup.com/333066/tsmc-2-nm-wafer-output-projected-to-reach-80-000-units-per-month-by-end-of-2025

[11] [News] Samsung Rumored to Mull on Scrapping 1.4nm Node to ... https://www.trendforce.com/news/2025/03/17/news-samsung-rumored-to-mull-on-scraping-1-4nm-node-to-prioritize-2nm3nm-yield-gains/

[12] Intel 18A yields at 20-30%? | SemiWiki https://semiwiki.com/forum/index.php?threads%2Fintel-18a-yields-at-20-30.22148%2F

[13] IEDM 2025 – TSMC 2nm Process Disclosure – How Does it... https://semiwiki.com/semiconductor-services/techinsights/352972-iedm-2025-tsmc-2nm-process-disclosure-how-does-it-measure-up/

[14] [News] Samsung Reportedly Achieves 30%+ Yield in SF2 Test ... https://www.trendforce.com/news/2025/02/07/news-samsung-reportedly-achieves-30-yield-in-sf2-test-production-set-for-q4-mass-prodution/

[15] Early 2025 industry survey shows 18A yields below 20-30 ... - Reddit https://www.reddit.com/r/intelstock/comments/1ix76kl/early_2025_industry_survey_shows_18a_yields_below/

[16] TSMC says 1.6nm chips will be in volume production in 2026 https://www.theregister.com/2025/01/16/tsmc_says_16nm_chips_volume_2026/

[17] Samsung to enter 2nm production in 2025, challenging TSMC https://www.digitimes.com/news/a20241217PD216/samsung-semiconductor-foundry-2nm-production-2025-tsmc.html

[18] [News] Intel Claims High-NA EUV Machines in Production with Good ... https://www.trendforce.com/news/2025/02/25/news-intel-claims-asmls-high-na-euv-machines-in-production-with-good-results-but-18a-yield-concerns-loom/

[19] [News] The 2nm Foundry Battle: TSMC Leads, Can Samsung and ... https://www.trendforce.com/news/2025/02/19/news-the-2nm-foundry-battle-tsmc-leads-can-samsung-and-intel-catch-up/

[20] Samsung's first 2nm process yield rates are quite promising (30%) https://www.reddit.com/r/hardware/comments/1ilo0cf/samsungs_first_2nm_process_yield_rates_are_quite/