Intel maintained its reign for so long that no one thought it could fail. Inevitably, it did. However, the comeback kid is here to play. In the AI arms race, Intel stands as the ultimate underdog. It is overshadowed by the likes of Nvidia and AMD, who have mastered marketing, yet quietly positioning itself as America’s semiconductor lifeline. Intel’s story is one of grit, reinvention, and strategic necessity. Let’s break it down.

Part 1: History

Intel’s origins trace back to July 18, 1968, when Gordon Moore and Robert Noyce founded the company in Santa Clara, California. Born from Fairchild Semiconductor alumni, it pioneered memory chips before dominating microprocessors with the x86 architecture. The 1971 Intel 4004, the world’s first microprocessor, ignited the PC revolution.

For decades, Intel ruled. Its “Intel Inside” campaign became synonymous with computing power. By the 1990s, it powered 80% of PCs worldwide, fueling Microsoft’s Windows empire. Under CEOs like Andy Grove, who coined “Only the Paranoid Survive,” Intel navigated antitrust scrutiny and competition from AMD, emerging stronger.

But hubris set in. Intel missed the mobile shift, ceding ground to ARM-based designs from Qualcomm and Apple. Foundry leadership slipped to TSMC and Samsung. By the 2010s, process node delays, which were stuck at 10nm while rivals hit 7nm, completely eroded its edge. Revenue peaked at $79B in 2021, but market share in data centers and AI dwindled as Nvidia’s GPUs surged.

Intel’s fall wasn’t overnight. It was a slow erosion of innovation amid complacency. Yet, its legacy as America’s chip pioneer endures, making its revival essential for national security.

Part 2: Recency Bias

Fast-forward to early 2025: Intel looked terminal. Stock plummeted below $20, layoffs hit 15,000, and every analyst whispered a sale, or bankruptcy. Despite $8.5B from the CHIPS Act in 2024 to boost U.S. manufacturing, execution faltered. Delays in fabs, mounting debt ($50B+), and fierce competition from TSMC and Nvidia painted a dire picture. The narrative completely shifted: Intel was a has-been, too big to pivot, and impossible to save.

Then came the turnaround. In March 2025, Lip-Bu Tan (LBT) took the helm, replacing ex-CEO, Pat Gelsinger. It reminds me of Tom Brady stepping in for Drew Bledsoe. The rest is history. Gelsinger’s vision was bold, but the execution lagged. LBT, a venture capital veteran from Walden International with deep semiconductor ties, has brought laser focus.

The game-winning drive unfolded.

August 2025: The Trump administration takes equity stake with CHIPS Act funding. September 2025: Nvidia invests $5B in Intel stock, signaling confidence in joint AI infrastructure. October 2025: SoftBank pledges $2B amid Q325 earnings surge. Stock rebounded and 18A ramped up. Recency bias had written Intel off, but reality has proved otherwise.

Part 3: The Underdog’s Edge

Today, Intel remains the underdog, but its growth narrative is shifting. No longer just a chipmaker eating into competitors via cost efficiencies (e.g., Lunar Lake CPUs undercutting AMD on power), it’s becoming a foundry powerhouse. That’s the pivot.

The single, most crucial business (that MUST grow and gain partnerships / customers) is IFS - Intel Foundry Services.

Intel’s foundry expansion is a core part of its IDM 2.0 strategy, launched in 2021, to regain semiconductor leadership by building a world-class foundry business. Credit must be given to Pat Gelsinger for the foresight, but he will ultimately be accredited with extremely poor execution.

It separates manufacturing (IFS) from product design, treating internal units as external customers for arm’s-length efficiency.

The goal: Compete with TSM / Samsung, secure US supply chain resilience, and target $8-10B annual savings by 2025 end. Investments exceed $100B over five years, creating 10K manufacturing and 20K construction jobs.

IFS is America’s greatest asset. In a world of geopolitical tensions, it hedges risks for smart players shifting from Taiwan to U.S. soil. TSMC’s Arizona fab is still tied to foreign control and vulnerabilities. Intel’s Ohio, Oregon, and Arizona expansions are domestic through and through, bolstering sovereignty in AI and beyond.

Part 4: The Roadmap Ahead

In one year, the market will no longer recognize Intel as “just a CPU company.” It will be running two AI-imperative businesses under one roof:

1. Intel Foundry Services (IFS): The world’s only American “pure-play foundry” at scale (with American IP and government stake).

2. Its own line of cost-effective AI accelerators that it can sell directly to Cisco, Google Cloud, AWS, Microsoft Azure, and the U.S. DoD. Intel will essentially have an entire TSM business, but also make AI chips that are cost-effective.

To understand the basics, let’s understand why you may hear the word “fab” referred to when speaking about TSM or Intel’s foundries. A foundry is called a fab because the actual factory that makes chips is short for “fabrication facility” (or fab for short). “Foundry” means a company manufactures chips for other companies (like a metal foundry casts parts for car makers).

For Intel, it owns both its foundry business (IFS, manufacturing for others) and its fabs (U.S.-based factories). Full vertical integration reduces Taiwan dependency, ensures supply chain control, and leverages government funding for leading-edge nodes like 18A, which is fully unique among U.S. players.

• Intel is American: Unlike TSMC (90%+ of advanced nodes in Taiwan), Intel operates 15 fabs across the US, Ireland, Israel, and beyond, with ~70% of capacity stateside. Its $20B+ CHIPS Act funding accelerates domestic expansion (e.g., Ohio, Arizona sites ramping to 18A by 2026), insulating against Taiwan Strait disruptions. In a blockade scenario, Intel’s output could surge 20-30% via repurposed legacy nodes, per analyst models.

• Geopolitical Tailwinds: US policy prioritizes Intel as a “national champion” is evidenced by the USG stake, and export controls favoring domestic fabs. A Taiwan crisis would trigger subsidies (potentially $50B+), boosting Intel’s market share in defense/AI chips while TSMC’s plants in America (e.g., Arizona) lag at <10% of capacity until 2028.

• Diversification Momentum: Intel’s foundry pivot (IFS) are attracting partners like MediaTek and Microsoft, reducing reliance on Asian suppliers. It sources only ~20% from TSMC (vs. Nvidia’s 100%), and recent talent poaching (e.g., TSMC exec Wei-Jen Lo) accelerates tech catch-up, per Reuters. This is instant leverage for derisking supply chains.

Apple, Nvidia, AMD, Broadcom, Qualcomm, AWS, Google, and Marvell design their own chips. They then hand the blueprints to TSM in Taiwan. TSM ships the packaged chips back, and those become the M-chips in your MacBook, the MI300 in supercomputers, the Snapdragon in Android phones, etc.

Risk management is the most imperative function in any organization, and in this industry, interim mechanisms must be implemented immediately aligning to a common taxonomy:

• Dual-sourcing mandates are already starting (Microsoft, Amazon, Google shifting portions to Intel 18A and / or Samsung 2nm).

• US government is forcing “friend-shoring” via CHIPS act, and now equity, covenants and export controls.

• Hyperscalers now model 12-24 month chip shortages in their scenario planning, driving accelerated qualification of Intel Foundry and TSMC Arizona as backstops.

Intel designs the chip, manufactures the chip, and ships the finished product itself (Core Ultra laptops, Xeon servers, Gaudi AI accelerators). No one else is involved. This is a moat.

Key Terms and what they mean:

• RibbonFET: Intel’s version of Gate-All-Around transistors (GAA). Think of it as wrapping the electrical “gate” completely around the channel instead of just three sides (FinFET). This results in far less leakage, way better efficiency, higher drive current - and the chips run faster and cooler.

• PowerVia: Intel flips the chip upside-down and delivers power from the back side. Frees up the front for more signal wires. 5-10% more transistors in the same area, with 4-6% higher performance at the same power.

• High-NA EUV: The next-generation lithography machines (cost $400M each). They use a bigger lens to print smaller features cheaper and with fewer steps. Intel will be the first foundry in the West to ship High-NA in volume (14A node).

• EMIB (Embedded Multi-die Interconnect Bridge): Intel’s clever way to glue multiple chiplets together side-by-side with tiny silicon bridges. Super-fast connection, and no giant expensive interposer like TSM’s CoWoS.

• Foveros: Intel’s true 3D stacking tech. Chips are stacked on top of each other with direct copper-to-copper bonding (face-to-face or face-to-back). This gives massive bandwidth, tiny footprint, and lower power vs. traditional packaging. This is how Intel will build monster AI systems and the base dies that everyone else stacks their chiplets on.

These last two (EMIB & Foveros) are the secret sauce that will enable Intel to beat TSM at advanced packaging today - and why Amazon, Google, Microsoft, and even Apple are quietly testing Intel’s lines.

In March 2021, Pat Gelsinger stood up and announced IDM 2.0, which was Intel’s ambitious plan to rebuild its process leadership while also turning itself into a serious external foundry. The idea was simple in theory and brutally hard in practice, “Make the best chips for itself while also manufacturing chips for the rest of the industry.”

Five years later, under new CEO Lip-Bu Tan, that vision is finally starting to look real. The company has become more disciplined about capital, more customer-focused, and a lot more honest about timelines. And the technology itself is now delivering.

Leading-Edge Nodes

Intel 18A family (≈1.8nm-class / angstrom-class)

• The first Western leading-edge node with RibbonFET (Gate-All-Around) with PowerVia (backside power delivery) manufactured at scale outside Taiwan / Asia.

• Entered high-volume manufacturing in the US in late 2025 / early 2026.

• Currently powering Intel’s own products (Core Ultra Series 3 “Panther Lake” client CPUs and Clearwater Forest Xeon).

• Yields continue to improve.

Key 18A variants:

• Intel 18A-P (Performance): High-performance variant optimized for compute/AI. Entered risk production (June 2026). Delivers ~9% higher performance at iso-power or ~18% lower power at iso-performance vs base 18A, plus significantly better thermal characteristics (up to 40% lower thermal resistance) and full design-rule compatibility.

• Intel 18A-PT: Specialized base die with backside power delivery, purpose-built for advanced 3D stacking. Supports pass-through TSVs, die-to-die TSVs, and hybrid bonding interfaces. Targeted at large multi-die AI systems and high-bandwidth 3DIC designs.

• Additional specialized variants (including low-power / mobile-optimized options and an 18A-U ultra variant mentioned in some roadmaps) for power-sensitive applications.

Intel 14A (1.4nm-class)

• This is the next major node after 18A. Features second-generation RibbonFET (RibbonFET 2) and advanced PowerDirect backside power.

• The official timeline under Lip-Bu Tan is risk production by late next year, into 2028, with high-volume manufacturing in 2029.

• 15–20% higher performance at iso-power or 25–35% lower power at iso-performance (projected gains vs 18A), with up to ~30% density improvement.

• Intel 14A-E (Enhanced): Further optimized variant offering additional performance/density gains (historically cited as ~5% extra in earlier roadmaps). Targeted for 2027–2029 timeframe depending on final customer pull.

Mature / Specialty Nodes

Tower Semiconductor partnership (65nm)

• A joint agreement was signed (announced in 2023) for Intel to manufacture Tower’s 65nm BCD (power management) and RF SOI technologies at Fab 11X in Rio Rancho, New Mexico.

• The partnership was aimed at automotive, industrial, defense, and power management markets, but as of early 2026, Intel has largely withdrawn from this manufacturing arrangement. Tower is shifting production elsewhere (Japan). The partnership is no longer a major active growth vector.

UMC collaboration

• This is a long-term partnership (announced Jan of 2024) to co-develop a 12nm FinFET process platform.

• Manufactured at Intel’s Arizona fabs (Ocotillo).

• Targets mobile, networking, communication infrastructure, and mixed-signal applications.

• Production expected around 2027. Leverages Intel’s US capacity and UMC’s foundry expertise and customer relationships.

• Discussions of deeper collaboration (including potential Super MIM capacitor tech licensing) have also surfaced.

18A Process: in detail

18A is the first true angstrom-class (roughly 1.8nm-class) process running at high volume in America. It is also the first commercial process in the world that combines Gate-All-Around transistors (RibbonFET) with backside power delivery (PowerVia).

This is the node that flips the script by providing:

• First true 2nm-class chip factory running at scale in America.

• Improved performance and reduced area, with PowerVia. Additionally, PowerVia has coarse pitch metals and bumps relocated to the back side of the die with PowerVia nano-TSVs in every standard cell.

  • PowerVia explained simply:
    Intel moved the power wiring to the back of the chip. Coarse-pitch metals and bumps are now on the backside, and tiny nano-TSVs bring power up into every standard cell. This frees up the front side for better signal routing.

    What this actually gives you:

    • 5-10% better density and cell utilization

    • Significantly lower IR drop and voltage droop

    • Roughly 4-6% more performance at the same power (Intel has cited up to 4% in some materials and higher in others)

    • RibbonFET Gate-All-Around transistors wrap the gate completely around the channel. This gives far better electrostatic control than old FinFET designs, which means better performance per watt and lower minimum operating voltage (Vmin).

    • Overall, PowerVia technology improves density and cell utilization by up to 5–10%, minimizes power-delivery droop, and delivers up to ~4% ISO-power performance improvement while greatly reducing IR drop compared to traditional front-side power routing.

• Full support for industry-standard electronic design automation (EDA) tools and reference flows for RibbonFET and PowerVia, enabling a smooth transition from other technology nodes and allowing customers to start designing with PowerVia ahead of other back-side power solutions.

  • All the popular design softwares (Cadence, Synopsys, Siemens) work out of the box with Intel’s new transistors and backside power. Most competitors won’t offer that for another 2-3 years.

• A robust assembly of more than 35 industry-leading ecosystem partners, providing capabilities across EDA tools, IPs, design services, cloud services, and aerospace and defense solutions, which helps ensure broad customer enablement to further ease adoption of Intel 18A.

  • Memory blocks, networking IP, security features, cloud design services, and defense-grade hardening), which someone else has already built and tested for 18A. It is plug and play.

RibbonFET GAA transistors (right) offer far better electrostatics compared to FinFET transistors (left) and offer an optimized ribbon architecture for outstanding performance per watt and Vmin.

PowerVia technology enhances density and cell utilization by up to 5 to 10 percent and minimizes resistive power-delivery droop, enabling an up to 4 percent ISO-power performance improvement and greatly reducing IR drop compared to conventional front-side power routing.

14A Process: in detail

While many still think Intel is just playing catch-up, 14A is already being shown to large potential customers. Early process design kits are out, and serious engagement is underway.

This process combines the next generation of both key technologies: PowerDirect & RibbonFET 2:

• Core upgrades in 14A:

  • PowerDirect is the 2nd-generation backside power delivery network. It is more efficient than the first-generation PowerVia, connecting power more directly to the transistors. This is a major contributor to the overall power and performance gains of the node.

  • RibbonFET 2 is the second-generation Gate-All-Around technology. It features tighter design rules for higher drive current, faster speeds, and better energy efficiency.

  • Turbo Cells are one of the more interesting new features. This is a boosted standard-cell technology that lets designers mix high-performance cells and more power-efficient cells inside the same design block. You can put the fast cells only on the critical paths (CPU max frequency and GPU critical paths) and use denser, lower-power cells everywhere else. This gives much better control over power, performance, and area for different parts of the chip.

  • High-NA EUV: Intel is among the first in the world to bring High Numerical Aperture Extreme Ultraviolet lithography into high-volume production. These advanced (and very expensive) tools allow finer features to be printed more cost-effectively with fewer multi-patterning steps.

• Expected gains vs 18A:

  • 15-20% higher performance at the same power

  • 25-35% lower power at the same performance

  • Up to ~30% better density

14A will be the world’s top node by 2027 / 2028 with the fastest, most efficient chips being made safely outside Taiwan.

Intel isn’t just making chips for its own laptops anymore. Its foundry will crank out the most advanced silicon and packaging on the planet for every high-stakes use case:

Memory

Intel’s engagement with memory technologies has been marked by ambition and adversity. In the early decades, the company pioneered dynamic random access memory, establishing foundational contributions to the semiconductor landscape. However, escalating competition from international manufacturers prompted a strategic retreat in 1985, redirecting resources toward microprocessor dominance. Subsequent efforts, such as the collaboration with Micron on flash memory, culminated in the introduction of 3D XPoint technology under the Optane brand.

This innovation sought to merge the speed of dynamic random access memory with the persistence of NAND storage, yet it encountered substantial hurdles, including elevated production expenses and limited market penetration. By 2022, Intel discontinued Optane development, incurring significant financial impacts, and divested its NAND operations to SK Hynix in stages.

These experiences accentuated the capital-intensive nature of memory markets, characterized by price volatility and reliance on specialized suppliers. Nevertheless, Intel preserved critical intellectual assets from these endeavors, including expertise in 3D stacking and material sciences, which now inform its current strategies.

At the heart of Intel’s revival lies Next Generation DRAM Bonding, a vertically stacked architecture developed under the United States Department of Energy’s Advanced Memory Technology (AMT) program. This technology layers eight or more dynamic random access memory strata, overcoming traditional constraints to deliver superior density, bandwidth, and energy efficiency.

Prototypes demonstrated in early 2026 validate its applicability to mission-critical environments, such as national laboratories and defense systems, emphasizing reduced dependency on international supply chains. Extending this foundation, Intel’s collaboration with SoftBank’s SAIMEMORY subsidiary advances ZAM, a next-generation solution promising two to three times the capacity of high-bandwidth memory, alongside halved power consumption.

Utilizing angled interconnects for optimized spatial efficiency, ZAM targets prototypes by fiscal year 2027 and commercialization by fiscal year 2029, aligning seamlessly with the artificial intelligence expansion trajectory.

IFS represents a cornerstone of the company’s strategic evolution, facilitating the convergence of advanced manufacturing processes with innovative memory technologies to deliver holistic solutions for artificial intelligence and high-performance computing applications. This division merges cutting-edge process nodes, such as Intel 18A and Intel 14A, with sophisticated packaging methodologies, including Embedded Multi-Die Interconnect Bridge (EMIB) and Foveros, to enable the seamless incorporation of ZAM into custom silicon designs. Such integration yields systems that minimize latency, optimize energy consumption, and reduce overall expenditures, thereby offering a compelling alternative to traditional, multi-vendor supply chains. By bundling processors, accelerators, and memory components, Intel provides streamlined offerings that may include advantageous pricing structures, particularly appealing to operators of large-scale data centers navigating constraints in advanced packaging availability.

The Intel 18A process node, which entered high-volume manufacturing in late 2025, stands as a pivotal achievement in this framework. As of February 2026, initial yield rates range from 55% to 65%, with projections indicating progression toward 65% to 75% throughout the year. This node incorporates RibbonFET gate-all-around transistors and PowerVia backside power delivery, enhancing power efficiency and transistor density to address the demands of artificial intelligence workloads. Building upon this, the Intel 14A node is advancing toward risk production in 2027 and volume manufacturing in 2028, featuring High Numerical Aperture extreme ultraviolet lithography for further refinements in performance and scalability. Customer commitments for Intel 14A are anticipated in the latter half of 2026 and the first half of 2027, underscoring the node’s external orientation and its potential to secure substantial foundry engagements.

Packaging innovations further amplify these synergies. The EMIB technology employs silicon bridges to interconnect chiplets within a package, while Foveros enables three-dimensional stacking, allowing memory layers to be positioned directly atop logic components. In the context of ZAM, these techniques facilitate vertical DRAM stacking with angled interconnects, achieving capacities two to three times greater than high-bandwidth memory equivalents, alongside power reductions of up to 50%. This architecture mitigates traditional bottlenecks in data movement, rendering it particularly suitable for artificial intelligence training and inference tasks that require high-bandwidth, low-power memory solutions.

Strategic alliances bolster the practical application of these technologies. Collaborations with entities such as Tower Semiconductor for analog processes, Synopsys for intellectual property portfolios, and United Microelectronics Corporation for 12-nanometer nodes expand Intel Foundry Services’ ecosystem, ensuring compatibility across diverse customer requirements. Notable engagements include custom artificial intelligence silicon development with Microsoft and Amazon Web Services, as well as exploratory discussions with Apple, Nvidia, and Advanced Micro Devices for advanced node utilization commencing around 2028. Additionally, partnerships with MediaTek highlight the adoption of EMIB as a cost-effective alternative to established packaging methods, addressing supply constraints in the sector. Government support through the CHIPS Act, including equity investments, further strengthens domestic manufacturing capabilities, aligning with national priorities for supply chain resilience.

These synergies position Intel as a versatile collaborator in high-performance ecosystems, enabling the creation of integrated artificial intelligence stacks that encompass Xeon processors, Gaudi accelerators, and next-generation memory. By mitigating reliance on fragmented sourcing and leveraging US-based fabrication, Intel enhances geopolitical stability and operational efficiency, fostering a pathway toward sustained leadership in specialized segments. While commercialization timelines for integrated solutions remain subject to yield optimizations and partnership finalizations, the foundational advancements underscore substantial potential for revenue expansion in artificial intelligence and high-performance computing domains.

Google’s evolution in TPU designs exemplifies the broader industry shifts benefiting Intel. Confronted with high-bandwidth memory scarcities and Taiwan Semiconductor Manufacturing Company’s capacity limitations, Google is reportedly transitioning variants like v8e to Intel’s EMIB technology through MediaTek. This move, evidenced by MediaTek’s recruitment of specialized engineers, signals cost-effective alternatives amid supply pressures, with potential extensions to hyperscaler’s like Meta. Google’s architectures necessitate central processing units for orchestration, harmonizing with Intel’s Xeon offerings. Incorporating ZAM could solidify Intel as a primary supplier for complete artificial intelligence stacks, diversifying Google’s dependencies and accelerating Intel’s market penetration.

Robotics

Today’s robots have evolved far beyond rigid, isolated machines. They now fuse cloud intelligence, edge processing, and AI to learn continuously and adapt in real time. Exponential technological progress is unleashing entirely new abilities and applications at an unprecedented pace¹.

With that, Intel is emerging as a robotics full-stack play through strategic investments, partnerships, and Xeon-powered hardware. With AI robotics, as a theme, catching steam in the markets, Intel’s bets position it for billions in the $210B market by 2030.

Intel Capital (its strategic venture capital arm) is aggressively backing humanoid robotics:

• Figure AI: $9M seed in 2023, which co-led $1B Series C (Sept 2025) with Nvidia and Salesforce, valuing Figure at $39B. Funds scaling general-purpose humanoids for warehouses and homes.

• RealSense Spinout: Intel carved out its AI vision arm, raising $50M for biometrics and robotics sensing.

• Physical AI Strategy: Intel Vision event spotlighted robotics / Physical AI as priority, leveraging Gaudi accelerators, edge compute for affordable humanoid bots, AVs, IoT.

These stakes secure Intel’s IP in next-gen bots, blending its edge AI with startups’ agility.

Intel’s latest Xeon 6 and recently launched Panther Lake processors are built for robotics:

• Humanoids: Xeon is integrated into its Robotics AI Suite² for up to 2x faster inference for real-time decisions. Xeon also powers Figure’s prototypes. Panther Lake enables cost-effective robot controls and AI perception.

• Manufacturing: Xeon W platforms (e.g., IMB-X1900 series) drive AI vision inspection and collaborative robots designed to safely work alongside humans using sensors to detect and avoid collisions in factories, cutting latency by 40%.

• Autonomous Vehicles: Custom Xeon AI chips in self-driving hardware through AWS cloud - already in AGVs / AMRs for logistics.

  • Mobileye: Intel’s autonomous driving subsidiary (acquired in 2017 for $15.3B), extends robotics via AV tech for robotaxis and commercial bots.

    Key Ties:

    • Robotaxi Partnerships: Mobileye Drive with VW, Rimac (Verne), Chinese OEMs for Level 4 / 5 autonomy in shuttles / vehicles, revealed during CES 2025.

    • Tech Integration: EyeQ6 / Ultra chips (on Intel 5nm) for vision, mapping (REM), AI in AVs / robotics, influencing edge AI for industrial bots.

• Nvidia-Intel collab (via its equity stake) enhances OpenVINO for robot AI, outpacing AMD in edge compute.

AWS / Google Cloud’s Xeon exclusivity locks in Intel’s hyperscaler volume, while robotics deals add $500M+ revenue streams.

Amid the whole AI hype, Intel’s 18A process validates its turnaround, where humanoids alone could hit $38B by 2035, according to Goldman Sachs.

Quantum Computing

Intel’s approach to quantum computing centers on silicon spin qubits, which utilize the spin states of electrons in silicon to encode quantum information. This methodology aligns with the company’s core competencies in transistor fabrication, enabling the production of quantum devices using established 300-millimeter wafer processes.

A pivotal development is the Tunnel Falls chip, a 12-qubit silicon spin qubit device introduced in 2023 and made available to research institutions to foster ecosystem growth. Tunnel Falls achieves high fidelity, with metrics such as 99.9 percent gate fidelity in single-qubit operations, positioning it as a foundational tool for advancing quantum research.

• Building on this, Intel continues to refine its quantum hardware. Recent efforts include enhancements in qubit density, uniformity, and error correction, essential for fault-tolerant systems. For instance, the company explores cryogenic control chips like Horse Ridge, which manage qubit operations at low temperatures, addressing scalability challenges in quantum systems. Future developments aim at million-qubit scales, with quantum dots serving as building blocks for dense, reproducible arrays. These initiatives reflect Intel’s commitment to bridging quantum and classical computing through hybrid architectures.

• Quantum Computing Ecosystem Layers

  1. Infrastructure: Foundational support for quantum hardware, including advanced cryogenics, vacuum systems, and shielding to preserve qubit stability.

  2. Quantum Processing: Core layer where quantum computations occur; dominant modalities include trapped ions, neutral atoms, superconducting circuits, and photons, with silicon spin qubits emerging strongly; also encompasses networking components like interconnects and quantum memories for distributed systems.

  3. Control and Readout: Interface managing classical-to-quantum translation, error handling, and result extraction.

  4. Middleware: Operational software stack, including programming languages, SDKs, compilers, optimizers, and schedulers.

  5. Applications: End-user layer with algorithms and software; currently challenging due to limited hardware power, but expected to capture significant value over time, similar to classical computing evolution.

• Intel’s quantum endeavors are amplified through strategic alliances that accelerate research and industrialization. A longstanding collaboration with QuTech, the quantum institute of Delft University of Technology and TNO, dates back to a $50 million investment in 2015, focusing on scalable quantum systems. This partnership has yielded advancements in spin qubit fabrication and control.

  In February, Intel signed a Memorandum of Understanding with Japan’s National Institute of Advanced Industrial Science and Technology (AIST) to develop large-scale silicon-based quantum computers, leveraging Intel’s manufacturing prowess for next-generation prototypes.

• Additionally, Intel joined the Chicago Quantum Exchange, collaborating with institutions to advance quantum engineering. These efforts extend to ecosystem partners like Quantum Machines, ensuring integrated solutions from hardware to software.

Intel Labs is working to achieve quantum practicality, the transition of quantum technology from the lab to commercial quantum systems that solve real-world problems. With the help of industry and academic partners, Intel has made significant progress in realizing this vision.

Intel is building a complete, manufacturable quantum computing stack centered on silicon spin qubits, leveraging its unmatched CMOS transistor expertise for scalability that most competitors lack. Goal: practical systems with >1 million qubits solving real problems in chemistry, materials, drug design, optimization, finance & cryptography. Here’s the comprehensive picture from Intel’s official research and key milestones.

Silicon Spin Qubits & Tunnel Falls

Intel’s core bet is silicon spin qubits in Si/SiGe quantum wells (isotopically purified for longer coherence times by reducing magnetic noise). Advantages vs superconducting qubits: much smaller devices, potential for “hot” qubits operating at higher temperatures (easier cooling/scale), and seamless integration with existing high-volume 300mm CMOS manufacturing. This enables the uniformity, yield, and cost curve needed for million-qubit systems.

Tunnel Falls, announced in June of 2023, is Intel’s most advanced silicon spin qubit chip released to researchers:

12-qubit device (linear array of 12 quantum dots). Fabricated on 300mm wafers at D1 fab using EUV lithography and advanced CMOS processes (gate/contact tech).

It achieved a ~95% yield across the wafer with voltage uniformity matching standard CMOS logic. Each wafer yields >24,000 quantum dot devices, while chips support 4–12 simultaneous qubits depending on config. Distributed via U.S. LPS Qubit Collaboratory to universities/national labs. Next-gen chip already in development (focus on quality/fidelity improvements, expected 2024+).

Argonne National Lab recently deployed this demonstrating CMOS-compatible quantum computing, and it validates high-volume manufacturing compatibility, which is a massive edge.

Cryogenic Control: Horse Ridge I & II (Solving the Wiring Bottleneck w/ QuTech)

Controlling thousands/millions of qubits from room-temperature electronics creates an impossible “interconnect/wiring bottleneck” (too many cables, heat, latency).

Horse Ridge series (developed with long-standing QuTech partner, which is a collaboration since around 2015):

Cryogenic quantum control chip placed inside the dilution refrigerator, right next to the qubits.

• 1st Gen was in 2020, with QuTech: First cryogenic control chip proof.

• 2nd-Gen Horse Ridge (debuted December 2020): Built on Intel’s 22nm FinFET Low Power technology. Integrates key control functions (microwave pulses for manipulation/readout). Dramatically reduces wiring complexity.

• 2021 Nature paper (Intel + QuTech): Demonstrated high-fidelity control and programmability of silicon qubits using Horse Ridge, which is a major milestone for scalable, reliable operation. This cryo-CMOS approach is foundational for scaling beyond hundreds of qubits.
  

Cryoprober: High-Volume Testing Engine for Commercialization

Traditional qubit testing (one device at a time in a cryostat) is too slow for process optimization at scale. Intel’s custom cryoprober (developed with Bluefors/AEM Afore) is a game-changer: fully automated cryogenic 300mm wafer prober cooling wafers to ~1.0K chuck / 1.6K electron temperature in ~2 hours.

It probes thousands of spin qubit arrays/quantum dot devices per wafer with machine vision alignment and programmable measurements (gate thresholds, mobility, noise sources, few-electron regime, etc.). Published in Nature (2024): “Probing single electrons across 300-mm spin qubit wafers.” Enables statistical wafer-scale data and rapid feedback loops for process tweaks — orders of magnitude faster than conventional methods. Directly accelerates path to reliable, high-volume quantum chip production. Intel calls it unlike any other tool and a key pillar (alongside Tunnel Falls + Horse Ridge II) for commercialization.

Intel Quantum Software Development Kit (QSDK)

Intel released QSDK v1.0 (Feb 2023; beta Sept 2022) — a full quantum computing stack in simulation that interfaces with real Intel hardware (Horse Ridge II + spin qubit chips as available).

Key features:

- Intuitive C++ programming interface (familiar to classical developers) via extended LLVM compiler toolchain with quantum extensions.
- Quantum runtime optimized for hybrid quantum-classical algorithms (QAOA, VQE, etc.) with seamless feedback loops between classical code and quantum results.
- High-performance Intel Quantum Simulator (IQS) backends (generic high-qubit or Intel hardware-specific simulation).
- Automatic mapping/scheduling of algorithms to qubits.
- Open-source Quantum Application Building Blocks repo on GitHub and Functional Language Extension for Quantum (FLEQ).
- VS Code extension for syntax support.
- Python/C++ integration for hybrid workflows.

It lowers the barrier for classical devs to experiment with quantum subroutines and prepares software for real hardware. This is not just a simulator, and it’s engineered as part of the full-stack path to commercial systems.

Major Progress & Strategic Edge

Intel has moved from isolated qubit demos to a validated full-stack approach:
- Silicon spin qubits on industrial 300mm CMOS processes with high yield/uniformity (Tunnel Falls).
- Cryogenic control integrated close to qubits
- High-volume characterization at cryo temps (cryoprober).

Mature hybrid software stack ready for devs and hardware (QSDK).

Focus is on quality (fidelity, coherence, uniformity via isotopic Si & process control) and manufacturability first, then aggressive scaling. This manufacturing moat (reusing/adapting world-class fabs) differentiates Intel from custom fab approaches by others. Still years from fault-tolerant million-qubit systems, but foundational engineering is advancing rapidly with real silicon results, published breakthroughs, and developer tools live today. Hybrid quantum-classical systems will integrate tightly with Intel’s classical AI/hardware strengths.

Intel isn’t chasing headlines with qubit counts alone. They never do chase headlines. They’re engineering a scalable, CMOS-native quantum platform from the fab up, which is control electronics, testing, software, and qubits. This positions them uniquely for when practical quantum advantage arrives. Long-term, the silicon spin qubit and full-stack strategy looks like one of the strongest plays in quantum hardware.

Part 5: The Tech Landscape Shift

• AI chips already use more electricity than 61% of the world’s countries.

• Training compute is exploding, and expected to grow more than 3× every year for the next decade.

• Compute power is growing so fast that memory bandwidth can’t keep up.

• Relying on one island in Taiwan for the world’s most advanced chips is no longer acceptable. Geographic diversity is now a national security and business survival issue.

• High-performance computing and AI designs are driving the majority of new foundry revenue.

• By 2028, chiplet-based designs will overtake traditional single-piece (monolithic) chips.

• Tomorrow’s best chips won’t come from making a better transistor alone, they’ll come from co-designing the entire system (silicon + packaging + software) from day one. This is Intel’s bread and butter.

  ---

Part 6: Emerging Partnerships and Rumors

Big things are happening under our very eyes…

As IFS gains momentum, partnership rumors are swirling, fueled by job postings and industry leaks that point to fabless giants diversifying from TSMC. These aren’t just whispers. They’re backed by concrete clues like specialized hiring, signaling trials and prep for production on Intel’s 18A node by year-end. Intel is actively distributing 18A process design kits (PDKs) to partners, pushing for fabless diversification amid geopolitical risks.

Apple

Apple’s rumors have ignited the latest buzz. Job listings for “DRAM Packaging Engineer” mention EMIB and 2.5D tech, suggesting potential IFS collaborations. Analyst Ming-Chi Kuo predicts Intel will manufacture Apple’s lowest-end M-series chips by mid-2027, marking an ironic return to partnership five years after Apple’s Intel breakup. This could leverage Intel’s 18A-P node for entry-level M chips, providing Apple a U.S.-based hedge against TSM/Taiwan risks. Shares surged Friday on the news, highlighting IFS’s potential breakthrough.

Among hyperscalers, current and potential partnerships amplify IFS’s edge.

Google

is deepening ties: Beyond Xeon 6 adoption for Cloud AI inference (delivering 1.38x boosts and 2x+ ROI), it’s evaluating EMIB for TPU v9 and beyond to bypass TSMC’s CoWoS constraints, booked through 2026. Google’s TPU v8e variant is planned to utilize Intel’s EMIB-T packaging technology, marking a shift from TSM CoWoS for this model. This aligns with reports of MediaTek securing orders for Google’s v7e and v8e TPUs and exploring EMIB to address CoWoS capacity constraints. Back in February, MediaTek was reported to place a major order of packaging wafers with Intel Foundry for TPU v8e.

MediaTek

is reportedly recruiting engineers experienced in Intel’s EMIB technology to support Google’s TPU production, indicating active collaboration. This is corroborated by industry analyses highlighting EMIB as a cost-effective alternative for large-scale artificial intelligence packages.

The adoption of EMIB-T for TPU v8e reflects broader industry trends where Intel’s advanced packaging gains traction amid TSMC’s supply tightness, potentially extending to other clients like for its MTIA chips, sources confirm Intel’s EMIB has been successfully implemented in its own products, positioning it for external growth. Meta is in discussions for MTIA accelerators using EMIB.

Cisco’s ecosystem integrations with Intel (e.g., via Broadcom’s VMware expansions) signal potential foundry plays, especially in networking and AI infrastructure.

These moves, alongside Amazon’s AWS commitments, position IFS as the resilient, domestic alternative for AI scale.

Tesla / SpaceX

plans to use Intel 14A process node for Terafab (SpaceX + xAI +Tesla). Elon Musk is calling it the right move as the node matures. He wants memory, logic, masks, and packaging under one roof for faster chip iteration. Memory here is a very key word. Intel Foundry also may have just won a portion of AI6 manufacturing, on top of the AI7 and beyond roadmap for Terafab, originally expected to be fabricated by TSM.

Intel is now one of the future beneficiaries for Tesla’s increased capex guidance. This is now a testament to Intel’s Foundry capabilities.

First, it helps to understand what Terafab actually is. Musk announced the project in March 2026 as a massive, vertically integrated semiconductor effort centered in Austin, Texas, near Tesla’s Giga Texas. The vision is straightforward but enormous: create a single complex that handles chip design, logic fabrication, memory, advanced packaging, and testing all under one roof. The goal is to reach one terawatt of annual compute capacity. To give that number some real weight, one terawatt of compute is roughly equivalent to the output of 100 to 200 million high-end AI chips per year. That is not a modest upgrade. It is an attempt to internalize and accelerate chip production at a scale that could rival or exceed large chunks of today’s global AI infrastructure. Early stages alone call for hundreds of thousands of wafer starts per month, with plans to scale toward a million. The result would be hundreds of billions of specialized chips annually. Tesla would use the output for its AI5 and AI6 chips that power Full Self Driving, Optimus humanoid robots, and future robotaxis. SpaceX and xAI would get specialized processors, including radiation-hardened versions, for satellite constellations, potential orbital data centers, and advanced AI workloads. By keeping everything close together, the project aims to speed up iteration cycles that are normally slowed by global supply chains and distant manufacturing.

On April 7th, the company posted on X that it was proud to join the Terafab project with SpaceX, xAI, and Tesla to help refactor silicon fab technology. Intel is bringing its most advanced 14A process node, which features gate all around transistors and backside power delivery for better performance and efficiency. It is also contributing its packaging expertise, including EMIB and Foveros technologies. In practice, Intel is acting as the foundry partner, providing the manufacturing know how and scale to help Terafab hit its targets faster. This is not just another customer deal. It gives Intel the large, long term anchor demand its foundry business has been chasing.

What really changes the story for Intel is how deeply the SpaceX piece is baked in. Reports suggest a significant portion of Terafab’s output, possibly as much as 80 percent in some early planning, is targeted at SpaceX needs. These are not ordinary data center chips. They are custom, radiation-hardened designs (sometimes referred to as D3 chips) built to survive the brutal environment of orbit and beyond: intense cosmic radiation, extreme temperature swings, vacuum conditions, and tight power budgets. Terafab will produce them at scale for the next generation of Starlink satellites, for future orbital data centers that could run AI workloads in space using solar power and radiative cooling, and potentially for deeper missions tied to Starship and Mars ambitions. Intel’s 14A technology and packaging strengths are exactly what make these resilient, high-performance space-grade processors possible.

That SpaceX involvement quietly turns Intel into a space play in its own right. For years investors have viewed Intel mainly through the lens of PCs, servers, and now terrestrial AI. Through Terafab, it now has direct exposure to one of the fastest-growing frontiers in technology: the infrastructure of space itself. The satellite boom, in-space computing, and multi-planetary ambitions are creating an entirely new class of demand for advanced semiconductors. Intel is no longer just supplying chips for Earth-bound data centers and autonomous vehicles. It is helping build the silicon backbone for humanity’s expansion off-planet. That diversification strengthens the entire thesis. It gives Intel a stake in the exploding space economy while feeding hard-won lessons from radiation-hardened designs back into its own roadmap for CPUs, GPUs, and AI accelerators.

The timing lines up with Intel’s own changes under CEO Lip Bu Tan. He has been streamlining the company with cost controls, targeted reductions in headcount, and a clearer focus on making Intel Foundry Services more independent and customer oriented. Intel is moving toward a hybrid model where it still designs its own Core, Xeon, and Gaudi AI products while also serving outside clients at scale. Terafab fits perfectly here. It validates the 14A node and gives Intel a high volume partner aligned with future growth areas like AI and robotics. In a world worried about supply chain security and geopolitics, Intel stands out as the major U.S. headquartered designer with true leading edge domestic production capacity. That combination of design capability and U.S. based fabs is rare and increasingly valuable.

For Intel, the advantages run deep. The partnership secures steady work that can help improve yields and attract more customers down the line. It also pulls Intel directly into the technologies shaping the next decade: autonomous agentic AI that can pursue goals on its own, fleets of humanoid robots, and compute systems tough enough for space. Tesla needs efficient, cost effective inference silicon to scale Optimus and push toward more reliable unsupervised driving. Intel gets real world feedback from these extreme use cases that can feed back into its own roadmap. In return, Tesla and SpaceX gain a more secure and responsive supply of chips made on American soil, which could accelerate timelines and reduce risks from overseas dependencies.

The bigger picture feels significant and frankly overlooked, and not understood. AI compute demand keeps rising as models grow, robots multiply, and new applications emerge in space and autonomy. Controlling the full manufacturing stack becomes a strategic edge. Terafab’s integrated approach promises quicker innovation than the traditional fragmented model. Intel’s involvement keeps much of that progress on U.S. soil with U.S. IP, which matters for national competitiveness and security. For Tesla specifically, the collaboration could help bring down the cost and improve the performance of the silicon needed for millions of Optimus units and widespread autonomous vehicles.

This is not a guaranteed smooth ride. Building at this scale involves real challenges around capital, yields, power, and talent. Yet the foundation is there: Intel’s 18A technology is already in production, its packaging strengths are proven, and the demand signal from Musk’s ecosystem is enormous. Intel has restructured itself around its manufacturing strengths at just the right moment. By teaming up with one of the most ambitious technology efforts underway, it is moving from a company fighting to regain footing to one helping build the silicon backbone for AI, robotics, and multi planetary ambitions.

In the end, Intel’s role in Terafab feels like a narrative of quiet resurgence. The company that helped define earlier eras of computing is now embedding itself in the infrastructure for agentic AI, humanoid machines, and the compute needs of space. Chip by chip, it is helping turn ambitious visions into working hardware. The road ahead will have hurdles, but the direction is clear. Intel is positioning itself to play a meaningful part in the future of space related AI chips and the autonomous design of silicon itself. That future looks genuinely promising.

Lucky #7, Part 7: D Day

Look, Intel is working with the whole Mag 7. Don’t forget that. Intel partners with every major neocloud, and these are major collaborations. Intel is staked by the most valuable company on the planet . It is staked by Softbank. It is staked by the US Government.

It is being backed by Elon Musk’s Tesla / SpaceXAI. Let us not lose sight of the fact that the most powerful people and institutions on the planet have Intel’s back. And Intel, themselves, have the superteam to execute on the backing. It is led by the most brilliant minds on the Executive team and one of the best CEOs in this space (no pun intended. the joke that never stopped).

This is America’s most valuable asset. It is the greatest company in the world, and somehow only a small % of people even understand what Intel is doing. The future of memory, the future of robotics, the future of Quantum Computing - these are all verticals that Intel has its grasps on. They have been researching and building on these areas for years. So, by the time it comes to fruition, Intel will be way ahead of everyone else. Except its investors. Only we will be there.

Intel will manufacture:

• Its own CPUs / GPUs

• Multiple AI accelerators (Amazon Trainium, Google TPU, Microsoft Maia, etc.)

• The most advanced mobile chips outside Taiwan

• All the secure chips the Pentagon needs

…all on American soil, with American IP, funded by American taxpayers, and completely vertically integrated.

A wise man once said, “the future is bright”.

Sources:

https://www.intel.com/content/www/us/en/learn/artificial-intelligence-robotics.html

So, X suspended my account because their automated system thinks I am a bot… “Authenticity” was the reasoning. I have had my “imnotharsh” account for 16 years. Paid for premium for 2 years. Have spent countless days researching and posting helpful content, and providing value. All gone. Even after a week of appealing every day, I keep getting denied. Yet, here we are. I have a lot to say and a lot to talk about. Especially related to Intel. I have not missed anything, but have not had the opportunity to speak to those on that platform.

Thankfully, Substack exists. Will use this platform to write for the few folks who either subscribe to me (thank you) or come across my content.

CURRENT PRICE: 133.99 ▲ +10.64% | VOL: 233.9M | MKT CAP: ~$673B (getting close to $1T).

TOP HEADLINES FROM JUNE, so far:

• President Trump announces Apple-Intel deal to design and manufacture chips in the U.S. (June 18, 2026)

• Intel shares surge to record high on Trump’s Truth Social post confirming Apple partnership (June 18, 2026)

  • President Trump publicly stated on Truth Social that “Apple has agreed to work with Intel to design and build its Chips in America.” This follows the U.S. government’s ~10% equity stake in Intel (announced 2025, now worth ~$60B) and Nvidia’s $5B investment. Intel shares jumped ~10-11% on the news, hitting a record close of $133.99 on June 18.

• U.S. government’s 10% stake in Intel now valued at ~$60B after recent gains (June 18, 2026)

• Intel foundry momentum builds with prior Google TPU order and Nvidia interest as backup (June 2026)

• Bank of America upgrade to Buy ($135 PT) on server CPU and foundry visibility (June 11, 2026)

• Semiconductor sector rally on onshoring narrative lifts INTC (June 18, 2026)

• High-volume breakout day as CHIPS Act efforts accelerate (June 18, 2026)

• Long-term AI infrastructure and advanced packaging thesis strengthened (June 2026)

  ---

A reminder back to Q1 2026 Earnings:

• Revenue: $13.6B (+7% YoY)

• GAAP EPS: $(0.73)

• Non-GAAP EPS: $0.29 (beat expectations)

• Foundry revenue grew; gross margins improved to 39.4% GAAP / 41.0% non-GAAP.

• Q2 2026 guidance: Revenue $13.8–14.8B; strong AI CPU and foundry momentum highlighted.

  ---

TECHNICAL ANALYSIS, EXPANDED (Multi-Timeframe)

Moving Averages Table
Daily: Strong breakout above 20/50/100DMA on June 18.
Weekly: Above key weekly averages.
Monthly: Bullish long-term structure.

Golden Cross: Active.
Bounces off MAs: Powerful breakout above recent resistance with massive volume.

Momentum Suite
RSI(14): 68+ (Bullish, approaching overbought)
MACD: Bullish crossover with expanding histogram
Williams %R: Overbought
Stochastic: Strongly bullish

HIGHLIGHTED COMBINED RSI + WILLIAMS %R STATUS: Overbought, with strong short-term momentum on positive news catalyst.

Volume Profile: Extremely high volume on June 18 breakout (233M+ shares). Clear institutional buying.

Unusual Options Flow (last 30 days): Elevated call volume during the rally. Call:Put ratio bullish.

Bollinger Bands (20,2): Upper band expansion. Price riding upper band. Bullish

TTM Squeeze: Off (expansion phase). Strong upward momentum. Squeezing Upward + Bullish

TMO (True Momentum Oscillator): Positive and rising sharply. Bullish

ST-EP06 Isotropic Trendline Assessment: Strong Uptrend. Normalized trend strength is robust after volatility adjustment — the June 18 breakout shows clear directional conviction.

Multi-Timeframe Rating: Bullish across daily/weekly/monthly.
Overall recommendation: Strong momentum confirmed by major catalyst.

- Expansion has started and the breakout is about to be wonderful -

SENTIMENT ANALYSIS:
Mentions exploded on the Apple deal news. Retail and institutional sentiment strongly bullish on foundry/AI narrative.

Call:Put ratio bullish (strengthening overall sentiment)

STRONG BUY.

Seems like we’re back to hating Intel.

By we, I mean folks who can’t seem to separate attachment to company from attachment to the stock price. a couple more days of consolidation and we see the haters pop out.

Remember, stock price doesn’t change the execution in real life. Conviction matters. Also, remember something else: Intel is America’s #1 asset in AI / chip dominance.

Here are the technicals for week ending 5/29 (Weekly):

One more week until the true test comes into play: Fight into my price discovery range.

The last 3 weeks, Intel has essentially flipped the fib resistance into support. It has actually found support at $114.50 and has seen buying at that level consistently in this consolidation phase.

• Strong bullish structure, with price in an uptrend channel still trying to enter Price Discovery

• All EMAs are rising

• RSI: 74.62 (elevated but bullish).

• Williams %R: -19.62 (short-term overbought).

• Strong upward sloping channel, with the price riding upper channel band, bullish continuation.

• Volume is heavy on rally.

  ---

The Daily chart shows this better:

Notice how it keeps defending the fib level (red line) the last 7 trading days, including today. The fib level is $114.43. Today, Intel closed at $114.68, above the level. The end of month rebalancing also caught a lot of people off guard.

• Bullish continuation on this consolidation and holding trend channel, above rising 20/50/100/200 EMAs.

• RSI is at 59.19 (showing healthy momentum)

• Williams %R is at -59.54 (neutral)

• TTM is green firing (bullish volatility expansion)

• Positive ascending channel, price holding mid-upper band after breakout.

• Volume is elevated.

Options Detail:

- Put/Call ratio is very low at 0.45-0.55 (well below 0.7 bullish threshold), heavily favoring call dominance. Call volume is heavy.

- Net GEX is strongly positive (~+$15M to +$97M per 1% move depending on source).

Call GEX dominates puts.

- Supports upward price pinning and momentum from recent heavy call buying.

- Stock volume is above average (150M+ shares today vs ~120M avg) - highly supportive.

Options Flow:

$600K in $165 calls 6/12/2026:

$5M in $135 calls 12/18/2026:

$3M Puts Sold (Bullish):

Bullish with the daily chart showing Intel is balanced with room to run. Support at $114, targeting $150 by next month.

Long. Live. Intel.

Intel’s partnership with Tesla, SpaceX, and xAI through Terafab marks a real turning point for the company. Earlier this month, after Elon Musk visited Intel’s campus, the two sides shook hands and made it official. Intel is now the key manufacturing partner in this ambitious semiconductor project. The move pushes Intel to sharpen its own operations while positioning it as the only major chip designer with leading edge U.S. based fabs and U.S. intellectual property. It is set to build and manufacture its own advanced CPUs and GPUs, and at the same time dive deeper into custom silicon for AI, agentic systems, robotics, and the harsh realities of space. Over time, Intel could become closely tied to the next wave of space related AI chips and autonomous chip design.

Terafab

First, it helps to understand what Terafab actually is. Musk announced the project in March 2026 as a massive, vertically integrated semiconductor effort centered in Austin, Texas, near Tesla’s Giga Texas. The vision is straightforward but enormous: create a single complex that handles chip design, logic fabrication, memory, advanced packaging, and testing all under one roof. The goal is to reach one terawatt of annual compute capacity. To give that number some real weight, one terawatt of compute is roughly equivalent to the output of 100 to 200 million high-end AI chips per year. That is not a modest upgrade. It is an attempt to internalize and accelerate chip production at a scale that could rival or exceed large chunks of today’s global AI infrastructure. Early stages alone call for hundreds of thousands of wafer starts per month, with plans to scale toward a million. The result would be hundreds of billions of specialized chips annually. Tesla would use the output for its AI5 and AI6 chips that power Full Self Driving, Optimus humanoid robots, and future robotaxis. SpaceX and xAI would get specialized processors, including radiation-hardened versions, for satellite constellations, potential orbital data centers, and advanced AI workloads. By keeping everything close together, the project aims to speed up iteration cycles that are normally slowed by global supply chains and distant manufacturing.

Intel joins Elon Musk’s TeraFab project — ‘Intel is proud to join the Terafab project with SpaceX, xAI, and Tesla to help refactor silicon fab technology’

Intel Centrality

On April 7th, the company posted on X that it was proud to join the Terafab project with SpaceX, xAI, and Tesla to help refactor silicon fab technology. Intel is bringing its most advanced 18A process node, which features gate all around transistors and backside power delivery for better performance and efficiency. It is also contributing its packaging expertise, including EMIB and Foveros technologies. In practice, Intel is acting as the foundry partner, providing the manufacturing know how and scale to help Terafab hit its targets faster. This is not just another customer deal. It gives Intel the large, long term anchor demand its foundry business has been chasing.

What really changes the story for Intel is how deeply the SpaceX piece is baked in. Reports suggest a significant portion of Terafab’s output, possibly as much as 80 percent in some early planning, is targeted at SpaceX needs. These are not ordinary data center chips. They are custom, radiation-hardened designs (sometimes referred to as D3 chips) built to survive the brutal environment of orbit and beyond: intense cosmic radiation, extreme temperature swings, vacuum conditions, and tight power budgets. Terafab will produce them at scale for the next generation of Starlink satellites, for future orbital data centers that could run AI workloads in space using solar power and radiative cooling, and potentially for deeper missions tied to Starship and Mars ambitions. Intel’s 18A technology and packaging strengths are exactly what make these resilient, high-performance space-grade processors possible.

The Space Game

That SpaceX involvement quietly turns Intel into a space play in its own right. For years investors have viewed Intel mainly through the lens of PCs, servers, and now terrestrial AI. Through Terafab, it now has direct exposure to one of the fastest-growing frontiers in technology: the infrastructure of space itself. The satellite boom, in-space computing, and multi-planetary ambitions are creating an entirely new class of demand for advanced semiconductors. Intel is no longer just supplying chips for Earth-bound data centers and autonomous vehicles. It is helping build the silicon backbone for humanity’s expansion off-planet. That diversification strengthens the entire thesis. It gives Intel a stake in the exploding space economy while feeding hard-won lessons from radiation-hardened designs back into its own roadmap for CPUs, GPUs, and AI accelerators.

The timing lines up with Intel’s own changes under CEO Lip Bu Tan. He has been streamlining the company with cost controls, targeted reductions in headcount, and a clearer focus on making Intel Foundry Services more independent and customer oriented. Intel is moving toward a hybrid model where it still designs its own Core, Xeon, and Gaudi AI products while also serving outside clients at scale. Terafab fits perfectly here. It validates the 18A node and gives Intel a high volume partner aligned with future growth areas like AI and robotics. In a world worried about supply chain security and geopolitics, Intel stands out as the major U.S. headquartered designer with true leading edge domestic production capacity. That combination of design capability and U.S. based fabs is rare and increasingly valuable.

For Intel, the advantages run deep. The partnership secures steady work that can help improve yields and attract more customers down the line. It also pulls Intel directly into the technologies shaping the next decade: autonomous agentic AI that can pursue goals on its own, fleets of humanoid robots, and compute systems tough enough for space. Tesla needs efficient, cost effective inference silicon to scale Optimus and push toward more reliable unsupervised driving. Intel gets real world feedback from these extreme use cases that can feed back into its own roadmap. In return, Tesla and SpaceX gain a more secure and responsive supply of chips made on American soil, which could accelerate timelines and reduce risks from overseas dependencies.

Back to the Future

The bigger picture feels significant and frankly overlooked, and not understood. AI compute demand keeps rising as models grow, robots multiply, and new applications emerge in space and autonomy. Controlling the full manufacturing stack becomes a strategic edge. Terafab’s integrated approach promises quicker innovation than the traditional fragmented model. Intel’s involvement keeps much of that progress on U.S. soil with U.S. IP, which matters for national competitiveness and security. For Tesla specifically, the collaboration could help bring down the cost and improve the performance of the silicon needed for millions of Optimus units and widespread autonomous vehicles.

This is not a guaranteed smooth ride. Building at this scale involves real challenges around capital, yields, power, and talent. Yet the foundation is there: Intel’s 18A technology is already in production, its packaging strengths are proven, and the demand signal from Musk’s ecosystem is enormous. Intel has restructured itself around its manufacturing strengths at just the right moment. By teaming up with one of the most ambitious technology efforts underway, it is moving from a company fighting to regain footing to one helping build the silicon backbone for AI, robotics, and multi planetary ambitions.

In the end, Intel’s role in Terafab feels like a narrative of quiet resurgence. The company that helped define earlier eras of computing is now embedding itself in the infrastructure for agentic AI, humanoid machines, and the compute needs of space. Chip by chip, it is helping turn ambitious visions into working hardware. The road ahead will have hurdles, but the direction is clear. Intel is positioning itself to play a meaningful part in the future of space related AI chips and the autonomous design of silicon itself. That future looks genuinely promising.

(Image: Intel factory workers working with a High NAEU lithography tool)

The Underdog’s Return

Intel has historically navigated complex dynamics within the semiconductor memory market, marked by periods of innovation, strategic exits, and recent re-engagement through partnerships and technological advancements. This thesis examines how Intel can revitalize its memory operations and emerge as a prominent player, particularly in the context of AI and high-performance computing (HPC) demands.

Partnerships with Sandia National Laboratories and SoftBank’s SAIMEMORY subsidiary, as well as shifts in Google’s Tensor Processing Unit (TPU) ecosystem, the analysis posits that Intel’s integrated foundry model, advanced packaging technologies, and next-generation memory architectures position the company to challenge the dominance of Micron Technology, SK Hynix, and Samsung Electronics.

By offering a unified solution encompassing memory, processors, and custom ASICs, Intel can address supply chain vulnerabilities, enhance performance efficiency, and capture market share in AI-driven workloads.

Lessons from the Past

Intel’s engagement with memory technologies has been marked by ambition and adversity. In the early decades, the company pioneered dynamic random access memory, establishing foundational contributions to the semiconductor landscape. However, escalating competition from international manufacturers prompted a strategic retreat in 1985, redirecting resources toward microprocessor dominance. Subsequent efforts, such as the collaboration with Micron on flash memory, culminated in the introduction of 3D XPoint technology under the Optane brand.

This innovation sought to merge the speed of dynamic random access memory with the persistence of NAND storage, yet it encountered substantial hurdles, including elevated production expenses and limited market penetration. By 2022, Intel discontinued Optane development, incurring significant financial impacts, and divested its NAND operations to SK Hynix in stages.

These experiences accentuated the capital-intensive nature of memory markets, characterized by price volatility and reliance on specialized suppliers. Nevertheless, Intel preserved critical intellectual assets from these endeavors, including expertise in 3D stacking and material sciences, which now inform its current strategies.

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The AI Memory Crunch

The rapid advancement of AI models has intensified demands on memory systems, exposing limitations in conventional technologies. Large-scale models require vast data handling, where traditional dynamic random access memory grapples with trade-offs between bandwidth and capacity, while high-bandwidth memory, integral to accelerators like Google’s TPU’s, faces supply shortages and power inefficiencies.

High-performance computing sectors, encompassing supercomputing and national security applications, necessitate low-latency solutions that prioritize energy conservation without compromising reliability. These pressures create fertile ground for alternatives that embed memory proximate to computational elements, thereby minimizing data transfer overheads and enhancing systemic efficiency. Intel’s initiatives address these precisely, targeting specialized segments where performance gains translate into competitive advantages.

Next Generation DRAM Bonding and Z-Angle Memory (ZAM)

Image: Blocks & Files

At the heart of Intel’s revival lies Next Generation DRAM Bonding, a vertically stacked architecture developed under the United States Department of Energy’s Advanced Memory Technology (AMT) program. This technology layers eight or more dynamic random access memory strata, overcoming traditional constraints to deliver superior density, bandwidth, and energy efficiency.

Prototypes demonstrated in early 2026 validate its applicability to mission-critical environments, such as national laboratories and defense systems, emphasizing reduced dependency on international supply chains. Extending this foundation, Intel’s collaboration with SoftBank’s SAIMEMORY subsidiary advances ZAM, a next-generation solution promising two to three times the capacity of high-bandwidth memory, alongside halved power consumption.

Utilizing angled interconnects for optimized spatial efficiency, ZAM targets prototypes by fiscal year 2027 and commercialization by fiscal year 2029, aligning seamlessly with the artificial intelligence expansion trajectory.

Image: Getty / Bloomberg

Competitive Landscape and Revival Strategy

Against Micron, SK Hynix, and Samsung, Intel’s differentiation lies in its foundry-memory synergy, domestic American production for geopolitical resilience, and focus on specialized AI / HPC segments. While the big three dominate commodity memory, Intel can target premium, custom solutions with ZAM’s efficiency gains. Revival requires:

• Scaling ZAM production through SoftBank’s investment and AMT insights.

• Expanding IFS customer base for integrated AI chips.

• Leveraging government contracts for initial adoption in secure applications.

• Offering bundled pricing to incentivize hyperscaler shifts.

Potential risks include delayed commercialization and competition from emerging technologies, but Intel’s progress in yields (over 60% for 18A) and sold-out 2026 CPU capacity signal momentum.

Foundry Synergy: Integrating Memory with Comprehensive Solutions

Intel Foundry Services represents a cornerstone of the company’s strategic evolution, facilitating the convergence of advanced manufacturing processes with innovative memory technologies to deliver holistic solutions for artificial intelligence and high-performance computing applications. This division merges cutting-edge process nodes, such as Intel 18A and Intel 14A, with sophisticated packaging methodologies, including Embedded Multi-Die Interconnect Bridge (EMIB) and Foveros, to enable the seamless incorporation of ZAM into custom silicon designs. Such integration yields systems that minimize latency, optimize energy consumption, and reduce overall expenditures, thereby offering a compelling alternative to traditional, multi-vendor supply chains. By bundling processors, accelerators, and memory components, Intel provides streamlined offerings that may include advantageous pricing structures, particularly appealing to operators of large-scale data centers navigating constraints in advanced packaging availability.

The Intel 18A process node, which entered high-volume manufacturing in late 2025, stands as a pivotal achievement in this framework. As of February 2026, initial yield rates range from 55% to 65%, with projections indicating progression toward 65% to 75% throughout the year. This node incorporates RibbonFET gate-all-around transistors and PowerVia backside power delivery, enhancing power efficiency and transistor density to address the demands of artificial intelligence workloads. Building upon this, the Intel 14A node is advancing toward risk production in 2027 and volume manufacturing in 2028, featuring High Numerical Aperture extreme ultraviolet lithography for further refinements in performance and scalability. Customer commitments for Intel 14A are anticipated in the latter half of 2026 and the first half of 2027, underscoring the node’s external orientation and its potential to secure substantial foundry engagements.

Packaging innovations further amplify these synergies. The EMIB technology employs silicon bridges to interconnect chiplets within a package, while Foveros enables three-dimensional stacking, allowing memory layers to be positioned directly atop logic components. In the context of ZAM, these techniques facilitate vertical DRAM stacking with angled interconnects, achieving capacities two to three times greater than high-bandwidth memory equivalents, alongside power reductions of up to 50%. This architecture mitigates traditional bottlenecks in data movement, rendering it particularly suitable for artificial intelligence training and inference tasks that require high-bandwidth, low-power memory solutions.

Strategic alliances bolster the practical application of these technologies. Collaborations with entities such as Tower Semiconductor for analog processes, Synopsys for intellectual property portfolios, and United Microelectronics Corporation for 12-nanometer nodes expand Intel Foundry Services’ ecosystem, ensuring compatibility across diverse customer requirements. Notable engagements include custom artificial intelligence silicon development with Microsoft and Amazon Web Services, as well as exploratory discussions with Apple, Nvidia, and Advanced Micro Devices for advanced node utilization commencing around 2028. Additionally, partnerships with MediaTek highlight the adoption of EMIB as a cost-effective alternative to established packaging methods, addressing supply constraints in the sector. Government support through the CHIPS Act, including equity investments, further strengthens domestic manufacturing capabilities, aligning with national priorities for supply chain resilience.

(Image: Intel)

These synergies position Intel as a versatile collaborator in high-performance ecosystems, enabling the creation of integrated artificial intelligence stacks that encompass Xeon processors, Gaudi accelerators, and next-generation memory. By mitigating reliance on fragmented sourcing and leveraging US-based fabrication, Intel enhances geopolitical stability and operational efficiency, fostering a pathway toward sustained leadership in specialized segments. While commercialization timelines for integrated solutions remain subject to yield optimizations and partnership finalizations, the foundational advancements underscore substantial potential for revenue expansion in artificial intelligence and high-performance computing domains.

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Google’s Pivotal Role: A Catalyst for Adoption

Google’s evolution in TPU designs exemplifies the broader industry shifts benefiting Intel. Confronted with high-bandwidth memory scarcities and Taiwan Semiconductor Manufacturing Company’s capacity limitations, Google is reportedly transitioning variants like v8e to Intel’s EMIB technology through MediaTek. This move, evidenced by MediaTek’s recruitment of specialized engineers, signals cost-effective alternatives amid supply pressures, with potential extensions to hyperscaler’s like Meta. Google’s architectures necessitate central processing units for orchestration, harmonizing with Intel’s Xeon offerings. Incorporating ZAM could solidify Intel as a primary supplier for complete artificial intelligence stacks, diversifying Google’s dependencies and accelerating Intel’s market penetration.

The Growth Horizon

This narrative illuminates Intel’s trajectory from memory retreat to prospective leadership, underpinned by innovations like ZAM and alliances that address artificial intelligence exigencies. By capitalizing on hyperscaler shifts and integrated offerings, like Google, Intel not only revives its memory operations but also fortifies its stature in the semiconductor domain. This understated evolution harbors substantial growth prospects, reshaping dependencies and fostering a robust, domestically anchored technology landscape.

Total cost of ownership (TCO) will likely erode margins for Nvidia and AMD, challenging assumptions of perpetual premium demand. True chip demand will quickly start reflecting ROI for buyers balancing performance, efficiency, and budgets in an increasingly competitive landscape.

This perspective underscores a shift toward more holistic valuations, where initial pricing gives way to comprehensive economic assessments over the lifecycle of technological investments.

Today’s AI systems are largely built on homogeneous architectures, vertically integrated with proprietary hardware, networks and software. This approach proves to be economically inefficient in the face of the increasing complexity of Agentic AI. To put this in perspective, an Agentic system can generate up to 100 times more tokens than a simple chatbot query, making the operating costs of homogeneous systems difficult to scale. This creates a major barrier to the widespread adoption of AI in businesses and everyday life [1].

Business Implications

What does the customer want to accomplish as a business?

Is performance going to exponentially increase with more expensive chips?

Are chips going to get cheaper and efficient?

Will chips increase lifespan?

Are businesses going to be in an upgrade cycle constantly?

Chips are indeed becoming cheaper and more efficient over time due to manufacturing advancements and economies of scale, yet this progress may not always justify premium pricing if alternative options deliver comparable outcomes at lower overall costs.

While chip lifespans are extending through improved durability and design, businesses often find themselves in constant upgrade cycles driven by software demands and competitive pressures, which amplifies the importance of selecting solutions that minimize disruption and maximize longevity.

Where it Matters

By selecting options with superior TCO profiles, buyers will likely enhance their own operational margins through reduced long-term expenditures, including lower energy consumption, minimized infrastructure needs, and extended hardware longevity, and in turn improving overall financial health and competitive positioning in their respective markets.

For data servers and vision models, soaring power and cooling costs, constrained rack space, persistent maintenance issues, and expiring warranties elevate total cost of ownership as a strategic enterprise lever. These factors should compel organizations to evaluate not only initial acquisition expenses but also ongoing operational burdens, such as electricity bills that can accumulate significantly over time and environmental compliance requirements that impose additional financial penalties for inefficient systems.

Comparative Analysis: The Intel TCO Method

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Introduction

Semiconductor packages serve as the foundational units in modern electronics, encapsulating chips that power devices from personal computers to data centers. As demands for computational power escalate, particularly with the proliferation of artificial intelligence applications, packages have grown in size and complexity. Traditional manufacturing methods for integrated heat spreaders, which are essential for dissipating heat generated by these chips, struggle to accommodate such scales. Conventional approaches rely on single-piece designs that require specialized, high-cost equipment, leading to production inefficiencies and thermal bottlenecks. The research in question proposes a novel disaggregated strategy to overcome these limitations, enabling more accessible and effective assembly while maintaining high performance standards.

Glossary of Key Terms

To facilitate a clearer comprehension of the advancements in integrated heat spreader assembly, the following glossary provides high-level definitions of central concepts. These explanations are tailored for those unfamiliar with the technical intricacies of chip manufacturing, emphasizing practical relevance over detailed engineering specifics.

• Semiconductor Package: A protective enclosure that houses one or more computer chips, along with supporting elements like wiring and connectors. It serves as the complete unit that integrates into devices such as computers or servers, ensuring the chips function reliably within larger systems.

• Integrated Heat Spreader (IHS): A specialized type of heat spreader that is directly attached to the chip package. It acts as a thermal bridge, spreading heat evenly across a larger surface to improve cooling efficiency, much like a radiator in an engine.

• Thermal Management: The overall strategy for controlling heat in electronic devices. This includes techniques to remove excess warmth generated by processing tasks, maintaining optimal temperatures to preserve performance and longevity.

• Disaggregated Approach: A modular design method that breaks down complex components, such as heat spreaders, into simpler, separate parts. This simplifies assembly, reduces costs, and allows for the use of standard manufacturing tools, contrasting with traditional one-piece constructions that require specialized equipment.

• Thermal Interface Material (TIM): A substance, often resembling a paste or pad, applied between the chip and the heat spreader. It fills microscopic gaps to enhance heat conduction, minimizing air pockets that could impede cooling.

• Package Warping: The unintended bending or distortion of the semiconductor package due to heat or mechanical stress. This can affect the flatness needed for proper heat transfer and overall functionality.

• Coplanarity: The degree to which surfaces within the package remain aligned and flat. High coplanarity ensures even contact between components, which is crucial for effective thermal performance and structural integrity.

• Stiffener: A reinforcing element added to the heat spreader or package to provide mechanical support. It helps maintain shape and flatness, particularly in larger designs where flexibility could lead to issues.

These terms collectively underscore the thesis’s focus on innovative assembly techniques that address challenges in producing larger, more powerful chip packages for demanding applications like artificial intelligence computing. By simplifying processes and enhancing efficiency, such advancements contribute to more accessible and sustainable semiconductor manufacturing.

Understanding Heat Spreaders in Semiconductor Technology

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1. Introduction

Quantum computing represents a paradigm shift in computational capabilities, promising to address complex problems beyond the reach of classical systems. , a leader in semiconductor manufacturing, has positioned itself as a key player in this emerging field by leveraging its expertise in silicon-based technologies.

This thesis examines Intel’s quantum computing initiatives, including its technological developments, investments through Intel Capital (their venture arm), collaborative efforts, competitive differentiators, potential future impacts, and strategies for capitalization. Drawing on recent advancements in the field, this thesis underscores Intel’s focus on scalable, manufacturable quantum solutions that integrate with existing infrastructure.

2. Technologies and Chips

Intel’s approach to quantum computing centers on silicon spin qubits, which utilize the spin states of electrons in silicon to encode quantum information. This methodology aligns with the company’s core competencies in transistor fabrication, enabling the production of quantum devices using established 300-millimeter wafer processes.

A pivotal development is the Tunnel Falls chip, a 12-qubit silicon spin qubit device introduced in 2023 and made available to research institutions to foster ecosystem growth. Tunnel Falls achieves high fidelity, with metrics such as 99.9 percent gate fidelity in single-qubit operations, positioning it as a foundational tool for advancing quantum research.

Building on this, Intel continues to refine its quantum hardware. Recent efforts include enhancements in qubit density, uniformity, and error correction, essential for fault-tolerant systems. For instance, the company explores cryogenic control chips like Horse Ridge, which manage qubit operations at low temperatures, addressing scalability challenges in quantum systems. Future developments aim at million-qubit scales, with quantum dots serving as building blocks for dense, reproducible arrays. These initiatives reflect Intel’s commitment to bridging quantum and classical computing through hybrid architectures.

The Tunnel Falls chip is shown here in packaging. (Credit: Intel Corporation)

3. Investments through Intel Capital

Intel Capital plays a crucial role in nurturing the quantum ecosystem by funding innovative startups. In February, Intel Capital participated in a $170 million Series C round for Quantum Machines, an Israeli company specializing in quantum control systems. This investment supports Quantum Machines’ platform, which serves over half of the companies developing quantum computers, enhancing control and orchestration capabilities essential for scalable systems.

Intel Capital’s strategy organizes the quantum industry into a five-layer stack, from quantum processing units to end-user applications, guiding investments across hardware, software, and enabling technologies. Additional commitments include support for error correction advancements, as emphasized in industry analyses, positioning Intel to benefit from broader quantum progress. These investments not only diversify Intel’s portfolio but also secure strategic access to complementary technologies that bolster its own quantum roadmap.

4. Lab to Fab - Intel’s Five Layer Stack

Quantum Computing Ecosystem Layers

1. Infrastructure: Foundational support for quantum hardware, including advanced cryogenics, vacuum systems, and shielding to preserve qubit stability.

2. Quantum Processing: Core layer where quantum computations occur; dominant modalities include trapped ions, neutral atoms, superconducting circuits, and photons, with silicon spin qubits emerging strongly; also encompasses networking components like interconnects and quantum memories for distributed systems.

3. Control and Readout: Interface managing classical-to-quantum translation, error handling, and result extraction.

4. Middleware: Operational software stack, including programming languages, SDKs, compilers, optimizers, and schedulers.

5. Applications: End-user layer with algorithms and software; currently challenging due to limited hardware power, but expected to capture significant value over time, similar to classical computing evolution.

Trends

• Quantum Error Correction: Industry consensus is shifting from scaling noisy systems to fault-tolerant designs. The growing focus is on error mitigation firms and advanced encoding techniques (e.g., quantum low-density parity-check codes).

• Rise of Middle-of-the-Stack Specialization: The move from full-stack models to ecosystem players excelling in specific areas (e.g., control systems like Quantum Machines, software tools like Classiq).

• Scale-Out Architectures: Increasing viability of linking multiple quantum processing units for distributed computing, potentially combining qubit types, though challenges remain in transduction, while scale-up innovations continue.

• Input-Output and Cryogenics Advances: Solutions addressing cabling heat / noise issues for large-scale qubit control, including denser connections, cryogenic electronics, and optical alternatives.

• Mergers and Acquisitions: Accelerating consolidation, with notable YTD activity by leaders acquiring assets across computing, interconnects, communications, and related fields, signaling strategic growth and exit paths for innovators.

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5. Partnerships and Collaborations

Intel’s quantum endeavors are amplified through strategic alliances that accelerate research and industrialization. A longstanding collaboration with QuTech, the quantum institute of Delft University of Technology and TNO, dates back to a $50 million investment in 2015, focusing on scalable quantum systems. This partnership has yielded advancements in spin qubit fabrication and control.

In February, Intel signed a Memorandum of Understanding with Japan’s National Institute of Advanced Industrial Science and Technology (AIST) to develop large-scale silicon-based quantum computers, leveraging Intel’s manufacturing prowess for next-generation prototypes.

Additionally, Intel joined the Chicago Quantum Exchange, collaborating with institutions to advance quantum engineering. These efforts extend to ecosystem partners like Quantum Machines, ensuring integrated solutions from hardware to software.

6. Differentiation from Competitors

Intel’s quantum strategy distinguishes itself through its emphasis on silicon spin qubits, which offer compatibility with existing CMOS manufacturing processes, unlike the superconducting circuits employed by competitors such as IBM, Google, and Rigetti.

IBM and Google focus on superconducting qubits for high-speed operations, achieving systems with hundreds of qubits, but face challenges in scalability due to custom cryogenic requirements. Rigetti, similarly, pursues hybrid quantum-classical systems with superconducting technology, emphasizing business-ready applications.

In contrast, Intel’s approach enables mass production using standard fabs, potentially reducing costs and improving yield uniformity. This silicon-centric model facilitates integration with classical processors, providing a unique pathway to hybrid computing that competitors may struggle to replicate without shifting paradigms.

Photo shows one of Intel's Tunnel Falls chips on a human finger to display its scale. Silicon spin qubits are up to 1 million times smaller than other qubit types. The Tunnel Falls chip measures approximately 50-nanometers square, potentially allowing for faster scaling. (Credit: Intel Corporation)

7. Future Impacts of Intel’s Quantum Technologies

The maturation of Intel’s quantum technologies holds profound implications for various sectors. By enabling efficient simulations of molecular interactions, these systems could revolutionize chemistry and materials science, accelerating drug discovery and catalyst design. In cryptography, quantum computers may render current encryption obsolete, necessitating quantum-resistant algorithms, while in optimization, they promise breakthroughs in logistics and finance.

Broader societal impacts include enhanced AI capabilities through quantum-accelerated machine learning, fostering innovations in predictive analytics and complex problem-solving. As quantum computing enters a utility era by 2025, Intel’s contributions could democratize access, driving economic growth and addressing global challenges like climate modeling.

8. Capitalization in Quantum

Intel is well-positioned to capitalize on quantum computing by integrating its chips into commercial ecosystems. By producing silicon spin qubits at scale using existing fabrication facilities, the company can achieve cost efficiencies and rapid iteration, outpacing rivals reliant on bespoke hardware. Hybrid models, combining quantum processors with classical ones, allow Intel to offer practical solutions for enterprise applications, such as those in AI and simulation.

Through Intel’s Quantum SDK, developers can prototype applications on simulators, transitioning seamlessly to hardware as it matures. Capitalization may involve licensing technologies, forming foundry services for quantum chips, or bundling with edge computing offerings, ensuring revenue streams as the market expands.

A magnified image of the Tunnel Falls chip. This chip has voltage uniformity similar to that achieved in a CMOS logic process. (Credit: Intel Corporation)

9. More to Go

Intel’s foray into quantum computing exemplifies a strategic fusion of legacy strengths with frontier innovation. Through silicon-based technologies, targeted investments, and collaborative networks, the company not only advances the field but also carves a distinctive niche amid intense competition.

As quantum systems evolve, Intel’s efforts promise transformative impacts, positioning the firm to lead in a quantum-enabled future. Continued progress will depend on overcoming error correction hurdles and securing broader adoption, yet the foundation laid today heralds significant potential for technological and economic advancement.

Sources

https://newsroom.intel.com/new-technologies/quantum-computing-chip-to-advance-research

https://www.bluequbit.io/blog/intel-quantum-computing

https://www.intelcapital.com/investing-in-the-foundation-of-quantum-computings-future-quantum-machines/

https://www.intel.la/content/www/xl/es/research/blogs/chicago-quantum-exchange.html

https://thequantuminsider.com/2025/02/07/aist-and-intel-strengthen-collaboration-for-industrialization-of-silicon-quantum-computers/

https://cen.acs.org/business/quantum-computing-chemistrys-next-AI/103/web/2025/11

1. What is OPEX?

OPEX stands for Options Expiration. It’s the day when options contracts officially expire. This happens on the third Friday of every month. On that day, people holding options have to decide what to do: exercise them (buy or sell the stock at the agreed price), close the position, or roll it over to a later date. This usually causes more trading activity and can make prices move around a bit more than usual.

Tomorrow, Dec 19th, will be OPEX and Quad Witch day.

2. What is Quadruple Witching (Quad Witch)?

Quadruple witching, or “quad witch,” is a bigger version of options expiration that only happens four times a year: the third Friday in March, June, September, and December.

On these days, four types of contracts all expire at the same time:

• Stock index futures

• Stock index options

• Single stock options

• (In the past, single stock futures too, but those aren’t really traded much anymore, so it’s basically three now)

People still call it “quad witch” even though it’s mostly three.

3. How Are OPEX and Quad Witch Connected?

“OPEX quad witch” just means the quarterly options expiration day when all those extra contracts (especially the index futures) expire together. Regular monthly OPEX is mostly about individual stock options, but the quarterly ones get a lot busier because of the added futures.

4. Why Does It Matter?

These days often see much higher trading volume, especially in the last hour of the day (sometimes called the “witching hour”). Traders are closing positions, rolling them over, or taking advantage of small price differences. This extra activity can push stock prices and indexes around more than on a normal day.

5. What Should You Know?

If you’re new to this, just remember: quad witching days can be choppy or volatile, but it’s not always crazy. If you have options or are watching stocks closely, keep an eye on volume and price action, especially toward the close.

The Bank of Japan (BoJ) is anticipated to raise its short-term policy rate by 25 basis points to 0.75 percent during its monetary policy meeting concluding on December 19. This adjustment would elevate rates to their highest level in three decades, continuing the normalization process initiated in prior years.

Market consensus is for a high probability to this outcome, with the current rate standing at 0.50 percent following a hold in October. The prevailing narrative emphasizes negative macroeconomic repercussions, primarily stemming from yen appreciation and the unwinding of yen carry trades, which have historically pressured global risk assets, including equities and emerging market securities.

2. The Case

Although the immediate rate hike may strengthen the yen in the short term, the critical determinant lies in the BoJ’s accompanying forward guidance. Should the central bank signal that further rate increases are paused or highly data-dependent, effectively communicating that 0.75 percent represents a near-term peak.

This could cap expectations of prolonged tightening. Recent analyses suggest the possibility that this hike may constitute the final significant move for an extended period, influenced by domestic economic softness, potential U.S. tariff impacts, and fiscal considerations. Such dovish signaling would differentiate the outcome from a hawkish continuation path, mitigating fears of unchecked yen strength.

3. The Impact

A clear indication of no additional hikes would likely stabilize or moderately weaken the yen post-announcement, alleviating pressure on carry trade positions. These trades, involving borrowing in low-yielding yen to invest in higher-return assets abroad, have faced forced unwinds amid prior normalization steps, contributing to volatility in global equities and bonds.

By removing the tail risk of multi-step tightening, the policy could foster a reconfiguration of positions without excessive liquidation, supporting risk appetite. This aligns with historical precedents where central bank pivot signals have bolstered asset prices by reducing uncertainty.

4. How It Could Be Positive Sentiment

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It now presents a compelling bullish case in the near term, supported by recent price action and technical indicators that suggest a potential reversal and continuation of the prior uptrend. As of today (12/17), with the stock trading around $37.31 intraday following a recent low near $36.92, several factors align to support a swift retest of the $44 to $45 zone, provided confirmation through a strong close above $38 today.

If Intel can peak above $38 today, it will start to flag, bullish, and run for another retest of the $44 resistance.

The most immediate catalyst is the decisive bounce from the vicinity of $36.95, a level that aligns closely with the observed intraday low and has acted as dynamic support.

This rebound occurred with conviction, as evidenced by the reversal in candlestick patterns and increased buying interest, preventing further downside penetration. The price defended a critical zone just below this level, incorporating elements of trendline support and prior consolidation lows.

Such a hard bounce from this area historically signals buyer dominance and often marks the initiation of a reversal, particularly in the context of an overarching uptrend from earlier 2025 lows around $18.

Let’s zoom in:

The price remains firmly above the 50-day, 100-day, and 200-day moving averages, reflecting sustained upward alignment established earlier in the year.

The 50-day average is positioned above the 100-day, which in turn exceeds the 200-day, maintaining the integrity of prior golden crosses (including the significant 50-day / 200 crossover observed mid-year). This configuration underscores the enduring primary uptrend from yearly lows near $18, providing a robust foundation for continued appreciation.

RSI / Williams

Momentum indicators further bolster this view. The RSI has shown values in the 45 to 57 range in recent sessions, positioned in neutral territory with upward momentum emerging from lower levels, allowing substantial room for appreciation without entering overbought conditions.

The Williams %R indicator, recently touching oversold readings near -85, is rebounding along an ascending trajectory consistent with the blue trendline. These placements on rising channels within the oscillators indicate building positive divergence and support the reversal narrative, as sellers exhaust near support while buyers regain control.

Structure

The current structure strongly resembles a bull flag formation. Following the impulsive rally to the December high near $44, the subsequent pullback has consolidated in a tightening range with higher lows, bounded by the upward trendline support (marked with multiple successful tests in the charts) and overhead resistance near recent highs. A healthy close above $38 today (ideally on elevated volume and away from the lows) would validate this breakout, confirming the flag’s resolution to the upside.

In classical TA, bull flag continuations typically project a measured move equivalent to the prior flagpole, positioning targets in the $44 to $45 region as a rapid retest of the prior peak. This aligns with the annotated resistance level in the primary chart and represents a logical objective given the stock’s momentum profile.

Combination of robust support defense near $36.95, improving oscillator trends, and potential bull flag validation positions Intel for accelerated upside. A confirmatory close above $38 would reinforce buyer conviction, paving the way for a prompt advance toward $44 to $45 in the coming sessions, consistent with the broader yearly uptrend. This setup warrants close monitoring for sustained strength above key moving averages and trendlines.

I expect a hard bounce and rally back to the resistance, but the question is, “what next?” If we make it past $44, we will likely see $50 quickly.

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I stated, “I am expecting $475 pretty quickly, and then a push past ATHs to close the year ~$500.” Guess what happened today? Tesla closed at its highest ever traded price of $489.88.

I could say, now that it has hit ATH’s, it will likely pullback. Probably. But, the odds are in the favor of a continued run-up to $530, if not higher. When Tesla is overbought, it tends to stay that way for a week.

Here is the updated chart. We have only touched ATHs, and not really broken out in a big way, yet. I could see $650 by June of next year. Tesla is volatile, so the path to get there will be one not for the faint-hearted.

The ticker now trades above its 8, 50, 200 MAs, and this ATH feat has occurred in a market that has not been forgiving to swing traders. It has been a frustrating 2 months, since October. Yet, seems to continue its push upward. Imagine what it will do when the market starts to rally again.

The following is a projected scenario based on price action, but things can change on a dime. The ticker is volatile, and the market has been nothing short of choppy.

If you did not read my prior 12/5 article, here is a reminder on what Tesla is capable of, historically.

Historical Moves:

-> Late 2016 to Jan 2017 (3-4 month consolidation): Surged +85% in 3 months after breakout, triggered by Model 3 production announcements.

-> Mid-2018 to Late 2019 (15 month consolidation): Exploded +400% in 4 months after breakout, driven by Q3 2019 earnings beat and China factory progress.

-> Early 2022 to Mid-2023 (18 month consolidation): Doubled +100% in 6 months after breakout, fueled by AI/Autonomy pivot and Q2 2023 deliveries beat.

-> Late 2023 to Early 2024 (4-5 month consolidation): Rose +70% in 9 months after breakout, spurred by Cybertruck launch and rate cut expectations.

-> Mid-2024 to Early 2025 (6 month consolidation): Rallied +130% in 4 months after breakout, catalyzed by Robotaxi unveil and earnings surge.

Average post-consolidation gain in these cases: Around 150% over 3-9 months, often massive due to TSLA’s leverage to news (e.g., 2020’s inclusion in S&P 500).

Call Options Volume / Net Premiums

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1. The Core Mechanism Driving the Divide

Every month, the Federal Reserve quietly adds tens of billions of new dollars to the banking system. It does this through repo operations, which means banks temporarily hand over Treasury bonds to the Fed and get fresh cash in return. The next day the trade reverses, but the Fed simply rolls it over again and again. The net result is the same as printing money, except it stays hidden on the balance sheet.

Quantitative Tightening (QT):

From mid-2022 until December 1st, 2025, the Fed was doing the opposite of printing money. Every month it let up to $95 billion of bonds mature without replacing them. That sucked cash out of the banking system and made reserves scarcer. Banks felt the squeeze, repo usage stayed low most of the time, and markets occasionally got nervous.

Why tomorrow’s FOMC matters:

QT officially ended on December 1st. The drain on bank reserves has stopped. In just the last week we have already seen repo operations jump above $13 billion as banks test the new, friendlier environment. Tomorrow, the Fed will likely confirm the end of tightening, lay out plans to buy roughly $45 billion of Treasury bills every month starting in 2026 (adding liquidity), and cut rates by 25 basis points. Powell’s tone will tell markets whether the money spigot is now wide open again.

This new cash lands first in the biggest banks. From there it flows straight into stocks, corporate bonds, and real estate because that is the fastest and safest way for banks and their clients to make a profit. Everyday people only feel the effects later, when rent, groceries, and gas prices go up. By then, stock and home prices have already jumped. The rich get richer first, and everyone else pays more for the same stuff.

2. How the Wealth Transfer Actually Happens

Think of it like a VIP line at a concert. The new money is the VIP ticket. Banks and big companies get in first and grab the best seats (stocks and property). Everyone else is stuck in the regular line paying higher prices for whatever is left.

Companies borrow at super-low rates and use the cash to buy back their own shares. In the 12 months through March 2025, S&P 500 companies spent almost $1 trillion doing exactly that. Fewer shares chasing the same profits means higher prices for anyone who already owns the stock.

Meanwhile, if you keep your money in a savings account or under the mattress, you lose ground every year. Official inflation is around 3%, but food, rent, insurance, and college costs are rising faster for most families. Even today’s 4-5% savings rates don’t keep up after taxes and the real cost of living.

3. The Cantillon Effect in Plain Sight

This isn’t new. It has a name from an 18th-century economist: the Cantillon Effect. Money always benefits the people closest to the source first.

The top 10% of Americans own 93% of all stocks. When the Fed adds liquidity, almost all the gains go straight to them. The bottom half of households own almost no stocks and live paycheck to paycheck. They just see higher bills at the grocery store and gas pump while their wages barely move. The gap between the “haves” and “have-nots” keeps growing, and the Fed’s actions are the main reason.

4. Why Productivity and “Fundamentals” Don’t Really Matter

It is cheaper and easier for a CEO to borrow money and buy back stock than to build a new factory. Building a factory takes years and might fail. Buying back stock lifts the price tomorrow and boosts the CEO’s bonus.

Real investment in machines, factories, and research is now only 13.8% of the economy, one of the lowest levels since World War II. At the same time, the stock market is worth more than twice the size of the entire U.S. economy, a level only seen at major market peaks.

Stocks are no longer priced on how much companies earn or produce. They are priced on how much new money the Fed keeps pumping in.

5. Outlook for 2026 and Beyond: More of the Same, Only Larger

The Fed has already stopped shrinking its balance sheet. Starting in 2026, it will add roughly $45 billion a month through Treasury bill purchases and repo operations. Interest rates are coming down, and the next Fed chair will almost certainly keep the liquidity flowing.

Company profits will grow a respectable 14% next year, but stock prices will rise even more because the “discount rate” keeps falling. Tech giants and growth stocks will lead again. The real economy might feel sluggish, with weak wage growth and struggling small businesses, but Wall Street won’t care as long as the Fed keeps the money tap open.

6. The Only Practical Conclusion

Cash is trash in this environment. Every year you hold it, you fall further behind.

Stocks, real estate in good locations, and other hard assets are the only reliable way to protect and grow your money right now. The Fed has made it clear: it will not let the financial markets crash, even if the broader economy slows down.

Own productive assets, stay invested through the noise, and accept the new reality: in today’s world, the stock market and the economy are two different things, and the stock market is the one the Fed is protecting.

For FOMC tomorrow, confirmed liquidity means banks flood risk assets, decoupling them from any economic wobbles like cooling labor data or sticky inflation, in which case I expect stocks to rally 5-10% into Q1 2026, echoing post-2008 QE legs where S&P doubled on similar easing. Sitting out guarantees you miss the tide that lifts boats for asset owners while the economy treads water.

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I am positioning for an upside surprise for FOMC this coming week and think it is the higher-reward play right now, especially if you have risk tolerance and a 1-4 week horizon.

Here’s why and how to think about it practically:

1. The baseline (25 bps cut + mildly dovish tone) is already ~95% priced (from Polymarket: https://polymarket.com/dashboards/fed-rates). That gives limited upside if Powell just meets expectations.

2. Any part of a dovish scenario of the dot plot showing 75+ bps in 2026, ~30-40% priced in many risk assets, would yield an immediate 3-8% pop in equities, 10-25% in crypto, and a sharp yield drop. That’s the asymmetric payoff.

Fed is cutting, we know that, but Powell’s words matter more than the 25bp cut itself. Like, if he says “Good Afternoon”. Jokes aside, if he sounds super dovish , we will be in a risk-on environment.

What super dovish means is if he says any of the following it will result in lower bond yields, weaker dollar, and a risk-on rally of equities:
- Signals easier policy ahead.
- Emphasizes weak labor market or low inflation risks over price pressures.
- Downplays need for restriction / hints at pausing only briefly.
- Stresses supporting growth / employment.

3. Downside protection is decent: even a “hawkish cut” (25 bps but dot plot sticks to 50 bps for 2026) would likely cause only a 2-4% pullback in the S&P and a 5-10% dip in Bitcoin, which is nothing that breaks the uptrend unless accompanied by a huge negative surprise elsewhere.

Risk / reward skew favors being long gamma or outright long into the meeting. Here are the trades you can make, depending on how risk aggressive you are:

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Golden Cross

Today, Tesla performed another golden cross (8MA / 50MA). It has already performed a prior golden cross (50MA / 200MA). Trending up - The last time this occurred, this was the move below (last November to mid-December). I have marked these with an ellipse, below.

Call Options Volume / Net Premiums

Immense buying pressure - tons of call volume over the last week - all expiring by January.

One buyer purchased $550C for 1/16 exp on 12/3 and volume carried over to OI. Since 12/3, OI has increased on this $550 call by 36k contracts.

Historical Moves:

-> Late 2016 to Jan 2017 (3-4 month consolidation): Surged +85% in 3 months after breakout, triggered by Model 3 production announcements.

-> Mid-2018 to Late 2019 (15 month consolidation): Exploded +400% in 4 months after breakout, driven by Q3 2019 earnings beat and China factory progress.

-> Early 2022 to Mid-2023 (18 month consolidation): Doubled +100% in 6 months after breakout, fueled by AI/Autonomy pivot and Q2 2023 deliveries beat.

-> Late 2023 to Early 2024 (4-5 month consolidation): Rose +70% in 9 months after breakout, spurred by Cybertruck launch and rate cut expectations.

-> Mid-2024 to Early 2025 (6 month consolidation): Rallied +130% in 4 months after breakout, catalyzed by Robotaxi unveil and earnings surge.

Average post-consolidation gain in these cases: Around 150% over 3-9 months, often massive due to TSLA’s leverage to news (e.g., 2020’s inclusion in S&P 500).

This time it is less about news as a catalyst, and more so the theme: Robotics / Autonomy is going to pick up some steam here in a couple weeks, while Tesla leads the sector.

I am expecting a volatile, violent move towards ATHs in a week or 2.

Santa needs his cookies.

Today’s robots have evolved far beyond rigid, isolated machines. They now fuse cloud intelligence, edge processing, and AI to learn continuously and adapt in real time. Exponential technological progress is unleashing entirely new abilities and applications at an unprecedented pace1.

With that, Intel is emerging as a robotics full-stack play through strategic investments, partnerships, and Xeon-powered hardware. With AI robotics, as a theme, catching steam in the markets, Intel’s bets position it for billions in the $210B market by 2030.

Investments Fueling Humanoid Ambitions

Intel Capital (its strategic venture capital arm) is aggressively backing humanoid robotics:

• Figure AI: $9M seed in 2023, which co-led $1B Series C (Sept 2025) with Nvidia and Salesforce, valuing Figure at $39B. Funds scaling general-purpose humanoids for warehouses and homes.

• RealSense Spinout: Intel carved out its AI vision arm, raising $50M for biometrics and robotics sensing.

• Physical AI Strategy: Intel Vision event spotlighted robotics / Physical AI as priority, leveraging Gaudi accelerators, edge compute for affordable humanoid bots, AVs, IoT.

These stakes secure Intel’s IP in next-gen bots, blending its edge AI with startups’ agility.

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Expanded weekly showing strong uptrend in rising blue channel from swing low (~$220) to swing high (~$470).

• Higher weekly lows over the last 3 weeks

  • Nov 16: 382.78

  • Nov 23: 383.76

  • Nov 30: 405.95

• Rising 50 / 200 SMA crossover

• Green volume spikes on breakout

• Fib retracement: Pullback hit 61.8% level (~$314) as support - bounced with doji hammer (long lower wick, tiny body near top), confirming golden ratio buy zone for continuation to $500 target by EOY

  

Tesla will retest recent highs, and then ATHs, first breaking 100% retrace ($474).

Arrow up means following the path up into close at end of each week. By mid-December we will see $475 (if not earlier).

• RSI at 52.10 signals neutral uptrend, bullish as it rises from oversold without overbought extreme.

• Williams %R (14) at -21.98 signals mild overbought (near highs, buy continuation).

• Stochs (14, 3, 3) at 76.06 / 69.27 shows momentum rising.

All supporting uptrend.

Note that Tesla often operates in overbought territory with violent uptrends.

From 2020-2025, daily:

• RSI > 70 19.8% of days overall

  • 23.8% in uptrends (close > SMA200)

• Average uptrend daily return: 0.20%, max consecutive gain: 38.3%

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Strong close for when Santa Clause comes to town. He must be fed chocolate chip cookies and whole milk.

1. The Moat

In one year, the market will no longer recognize Intel as “just a CPU company.” It will be running two AI-imperative businesses under one roof:

1. Intel Foundry Services (IFS): The world’s only American “pure-play foundry” at scale (with American IP and government stake).

2. Its own line of cost-effective AI accelerators that it can sell directly to Cisco, Google Cloud, AWS, Microsoft Azure, and the U.S. DoD. Intel will essentially have an entire TSM business, but also make AI chips that are cost-effective.

To understand the basics, let’s understand why you may hear the word “fab” referred to when speaking about TSM or Intel’s foundries. A foundry is called a fab because the actual factory that makes chips is short for “fabrication facility” (or fab for short). “Foundry” means a company manufactures chips for other companies (like a metal foundry casts parts for car makers).

For Intel, it owns both its foundry business (IFS, manufacturing for others) and its fabs (U.S.-based factories). Full vertical integration reduces Taiwan dependency, ensures supply chain control, and leverages government funding for leading-edge nodes like 18A, which if fully unique among U.S. players.

What does that look like? Semivision created a great visual on this distinction.

Apple, Nvidia, AMD, Broadcom, Qualcomm, AWS, Google, and Marvell design their own chips. They then hand the blueprints to TSM in Taiwan. TSM ships the packaged chips back, and those become the M-chips in your MacBook, the MI300 in supercomputers, the Snapdragon in Android phones, etc.

Intel designs the chip, manufactures the chip, and ships the finished product itself (Core Ultra laptops, Xeon servers, Gaudi AI accelerators). No one else is involved. This is a moat.

2. Key Terms (and what they actually mean)

• RibbonFET: Intel’s version of Gate-All-Around transistors (GAA). Think of it as wrapping the electrical “gate” completely around the channel instead of just three sides (FinFET). This results in far less leakage, way better efficiency, higher drive current - and the chips run faster and cooler.

• PowerVia: Intel flips the chip upside-down and delivers power from the back side. Frees up the front for more signal wires. 5-10% more transistors in the same area, with 4-6% higher performance at the same power.

• High-NA EUV: The next-generation lithography machines (cost $400M each). They use a bigger lens to print smaller features cheaper and with fewer steps. Intel will be the first foundry in the West to ship High-NA in volume (14A node).

• EMIB (Embedded Multi-die Interconnect Bridge): Intel’s clever way to glue multiple chiplets together side-by-side with tiny silicon bridges. Super-fast connection, and no giant expensive interposer like TSM’s CoWoS.

• Foveros: Intel’s true 3D stacking tech. Chips are stacked on top of each other with direct copper-to-copper bonding (face-to-face or face-to-back). This gives massive bandwidth, tiny footprint, and lower power vs. traditional packaging. This is how Intel will build monster AI systems and the base dies that everyone else stacks their chiplets on.

• These last two (EMIB & Foveros) are the secret sauce that will enable Intel to beat TSM at advanced packaging today - and why Amazon, Google, Microsoft, and even Apple are quietly testing Intel’s lines.

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3. The IFS Roadmap

In 2021, Intel’s ex-CEO Pat Gelsinger announced the “IDM 2.0” strategy, outlining ambitions to build a world-class foundry business alongside its core chip design. Under new leadership from Lip-Bu Tan, execution is accelerating,

• 18A (sub 2nm-class, first Western leading-edge node outside Taiwan)

  • Intel 18A-P (high-performance variant optimized for compute/AI).

  • Intel 18A-PT (extension for 3D die stacking via Foveros Direct hybrid bonding. For large AI systems).

  • New specialized nodes for Intel 18A (tailored variants for mobile/low-power apps).

• 14A (1.4nm-class, with risk production next year into 2027. 15-20% performance/watt gain over 18A)

  • Intel 14A-E (enhanced version, 2027 onwards, with further optimizations for density and speed).

• Mature Nodes (for analog/RF/legacy apps, joint development with Tower Semiconductor)

  • 65-nanometer process (high-yield, cost-effective, expected next year for automotive/defense).

  • Additional collaborations like 12nm/16nm with UMC for mixed-signal derivatives.

18A Process

This is the node that flips the script by providing:

• First true 2nm-class chip factory running at scale in America.

• Improved performance and reduced area, with PowerVia. Additionally, PowerVia has coarse pitch metals and bumps relocated to the back side of the die with PowerVia nano-TSVs in every standard cell.

  • Intel moved the power wiring to the back of the chip (PowerVia). That alone squeezes 5-10% more transistors into the same space and gives you roughly 4-6% more speed at the same power.

• Full support for industry-standard electronic design automation (EDA) tools and reference flows for RibbonFET and PowerVia, enabling a smooth transition from other technology nodes and allowing customers to start designing with PowerVia ahead of other back-side power solutions.

  • All the popular design softwares (Cadence, Synopsys, Siemens) work out of the box with Intel’s new transistors and backside power. Most competitors won’t offer that for another 2-3 years.

• A robust assembly of more than 35 industry-leading ecosystem partners, providing capabilities across EDA tools, IPs, design services, cloud services, and aerospace and defense solutions, which helps ensure broad customer enablement to further ease adoption of Intel 18A.

  • Memory blocks, networking IP, security features, cloud design services, and defense-grade hardening), which someone else has already built and tested for 18A. It is plug and play.

RibbonFET GAA transistors (right) offer far better electrostatics compared to FinFET transistors (left) and offer an optimized ribbon architecture for outstanding performance per watt and Vmin.

PowerVia technology enhances density and cell utilization by up to 5 to 10 percent and minimizes resistive power-delivery droop, enabling an up to 4 percent ISO-power performance improvement and greatly reducing IR drop compared to conventional front-side power routing.

14A Process

While many think Intel playing catch-up, 14A is already being shown to large customers.

This process combines PowerDirect with RibbonFET 2:

• PowerDirect is the 2nd generation of backside-power delivery network.

  • Upgraded backside power wiring: even more efficient than the first version, cutting power waste by 25-35%.

• RibbonFET 2 is the 2nd generation of gate-all-around technology.

  • Tighter design for faster speeds and lower energy use.

• Turbo Cells introduced, which is a boosted cell technology further enhancing speed (including CPU maximum frequency and GPU critical paths) when paired with RibbonFET 2. Turbo Cells allows designers to optimize a mix of more performant cells and more power-efficient cells within a design block, enabling a tailored balance between power, performance, and area for target applications.

  • Lets designers blend super-fast parts with power-saving ones in the same chip: customize for max speed in key spots (like CPU/GPU cores) without wasting energy elsewhere.

• Industry First High Numerical Aperture (High NA) EUV, enabling cost-effective printing of smaller process features.

  • First Western use of advanced $400M printers: makes tiny features cheaper and easier than rivals.

14A will be the world’s top node by 2027 - fastest, most efficient chips - made safely outside Taiwan.

4. What IFS Actually Builds (and for Whom)

Intel isn’t just making chips for its own laptops anymore. Its foundry will crank out the most advanced silicon and packaging on the planet for every high-stakes use case:

• AI accelerators (TPUs, DPUs, NPUs)

• Data-center CPUs & GPU

• Networking & storage chips

• 3D-stacked “base dies” (The foundation tiles that let companies glue multiple chips together into monster AI systems)

• Cryptocurrency ASICs (Yes, even those)

• Defense & aerospace (Secure, US-made silicon the Pentagon can actually trust)

4a. Why IFS Is Massive for America (and Customers)

• Taiwan Risk vanishes overnight: 18A is the earliest 2nm-class node you can buy that is not made on a seismically active, geopolitically contested island.

• Pricing power flips: Once Intel hits 80%+ yields on 18A (expected mid-2026), it can undercut TSM on price while keeping the profits in the U.S.

• National security lock-in: DoD and intelligence agencies will mandate U.S.-made leading-edge silicon. Intel is the only option.

• Customers win twice: They get TSM-level (or better) silicon, sleeping better at night knowing their supply chain won’t disappear if China invades Taiwan.

5. The Tech Landscape Shift

• AI chips already use more electricity than 61% of the world’s countries.

• Training compute is exploding, and expected to grow more than 3× every year for the next decade.

• Compute power is growing so fast that memory bandwidth can’t keep up.

• Relying on one island in Taiwan for the world’s most advanced chips is no longer acceptable. Geographic diversity is now a national security and business survival issue.

• High-performance computing and AI designs are driving the majority of new foundry revenue.

• By 2028, chiplet-based designs will overtake traditional single-piece (monolithic) chips.

• Tomorrow’s best chips won’t come from making a better transistor alone, they’ll come from co-designing the entire system (silicon + packaging + software) from day one. This is Intel’s bread and butter.

By 2027, Intel will manufacture:

• Its own CPUs / GPUs

• Multiple AI accelerators (Amazon Trainium, Google TPU, Microsoft Maia, etc.)

• The most advanced mobile chips outside Taiwan

• All the secure chips the Pentagon needs

…all on American soil, with American IP, funded by American taxpayers, and completely vertically integrated.

A wise man once said, “the future is bright”.

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You may not be aware that Intel and AWS are partnering to provide optimized performance, efficiency, and scalability. Leveraging AI inferencing at the edge, powered by AWS and Intel, organizations can achieve real-time analysis and decision-making without the latency of data center trips.

Intel’s advanced CPU tech drive cost-effective GenAI and machine learning workloads on AWS. There is a large focus at this event on how, with the right models, tooling, and deployment strategy, Intel CPUs on AWS can unlock powerful AI capabilities without the GPU premium.

The event will discuss what mass media seemingly purposely ignores, which is the partnership that Amazon and Intel have.

Why is it not being talked about?

- Private/closed-door format limits leaks and is overshadowed by the flashy Nvidia / Anthropic announcements.

- Media prioritizes consumer AI hype over B2B supply chain shifts. Intel’s involvement (speculated via prior Microsoft / Amazon IFS ties) stays under the radar until formal wins.

- Massive asymmetry: Positions Intel as quiet hedge in $7T data center boom.

Why is this important for Intel?

- Intel’s IFS (Foundry Services) aligns with AWS’s push for diversified, US-based AI chip production.

- Trainium2 could tap Intel’s 18A node for high-volume, low-latency inference, reducing TSM reliance.

- If validated, it secures multi-billion contracts, boosts IFS revenue (target $15B+ by 2027), and leverages CHIPS Act subsidies for domestic fabs, amplifying AI pivot amid Taiwan risks.

Agenda Topics (Roundtables)

- Where and how CPUs can be effectively used in AI pipelines, from data preprocessing to inference.

- Real-world use cases where CPU-based architectures outperform or complement GPU-heavy environments.

- Pricing comparisons between CPU and GPU instances on AWS, and how to optimize for Total Cost of Ownership (TCO) without compromising performance.

- Best practices and strategies for modernizing workloads, including mainframe and legacy code, to run efficiently on CPU-based infrastructure.

Link to event: https://registration.awsevents.com/flow/awsevents/reinvent2025/eventcatalog/page/eventcatalog?search=intel

Intel continues to defeat the hate and outperforms, despite yet-to-be validated IFS customers - the likes of Qualcomm, Apple, Broadcom, and MediaTek - all either searching for EMIB specific engineers, or in the rumor mill elsewhere. Its greatest catalysts will come from these announcements.

The close for the last 5 months:
Jul - $33.00
Aug - $34.50
Sep - $36.20
Oct - $38.10
Nov - $40.56

Delta, Nov/July: +23.0%

This is is YTD - bounced off of upward trendline - and closed $3 clear of the 50 MA. Bullish sentiment and price action. Uptrend momentum, building support with higher monthly lows.

Institutional Ownership:

- 64.5% of float held by institutions (up from ~60% earlier YTD), with active rotation.
- Funds adding positions amid AI / foundry bets. Quarterly 13F states net +1-2% accumulation.

Call Option Volumes:

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