Welcome to Inner Journey - Reflections Within Series - Article #8 !
In the previous article Inner Journey - Reflections Within - Article #7 , I shared my understanding and reflections on Chapter 2, Verse 6. Continuing this journey, in this article I explore Chapter 2, Verse 7 through the shloka, its direct meaning, commentaries, and its relevance to our everyday lives.

Let’s get started !

The commentaries shared here are not my original work. They are the result of studying and learning from various sources, which I have consolidated and presented based on my current understanding. This article is therefore a reflection of my learning journey rather than an authoritative interpretation.

Verse 7

कार्पण्यदोषोपहतस्वभाव:
पृच्छामि त्वां धर्मसम्मूढचेता: ।
यच्छ्रेय: स्यान्निश्चितं ब्रूहि तन्मे
शिष्यस्तेऽहं शाधि मां त्वां प्रपन्नम् ॥ 7॥

Meaning

Arjuna says : My inner character has been afflicted by weak, petty thoughts. My intellect is clouded. I am confused/bewildered by dharma and adharma. Hence I ask of you to tell me with certainty what is best for me. I am your student/disciple. I have surrendered unto you. Please instruct me.

Commentary

For the first time Arjuna realizes and agrees that he is confused. He is willing to change his thoughts; his decision. Unless there is a willingness to learn/change, a teacher’s wisdom is useless. It shows the attitude of Arjuna to seek guidance from Krishna. Arjuna who is a friend of Krishna now offers himself to Krishna as a disciple. Duryodhana on the other hand was not willing to listen to Krishna’s advise. Duryodhana was unwilling to listen to what is right and what is wrong. Duryodhana in a way represents the human eternal problem of doing wrong in spite of knowing that it is wrong. It could have been lust, greed, hate and anger which pushed him towards wrong doings.

We have also ruined our minds by dumping trash like prejudice, desire, greed etc. into it.

The word kripana in this verse means people with petty thoughts. The kripanas are people who are caught up with the material things in life, without understanding the science of self-realization.

Modern-Time Relevance

In our everyday lives, we often face situations where we are unsure about what the right thing to do is. We may have conflicting thoughts, emotions, expectations, or responsibilities, and sometimes we may not even be willing to admit that we are confused.

Arjuna's attitude in this verse teaches us that acknowledging our confusion is not a weakness. In fact, it is the first step towards clarity. Once we accept that we do not have all the answers, we become open to learning and receiving guidance.

The verse also reminds us that having a good teacher, mentor, parent, friend, or well-wisher is valuable only when we are willing to listen. Advice can be offered to us, but unless we are prepared to reflect on it and, if necessary, change our way of thinking, that wisdom cannot truly help us.

This verse also makes us reflect on our willingness to do what is right. The challenge is not merely knowing the difference between right and wrong, but having the clarity and strength to choose what is right.

A Prayer from GitaDaily.com — Inspired by Chapter 2, Verse 7

Dear lord, bless me to remember that no matter how confusing or confounding my situation is, you are always there for me to turn to.

Even when it is difficult to know what is the right thing to do, let me be grateful that I still have the desire to do the right thing.

Bless me O lord, so that I can see your blessing even in situations when I see no blessing. Even when life confounds me, thrusting me into dilemma where no way seems to be the right way, let me remember that there remains one right way for me - one that nothing in the world can ever take away from me. That right way is to turn to you, O lord, who can find a way through even the messiest of situations.

Help me to remember that you and you alone are with me through all of life’s turbulences, even those that take away my intelligence to know the right thing to do. Bless me, O lord, so that no matter what I lose, I may never lose the intelligence to turn towards you.

Let the confusion in the world never disconnect me from you. Let it only increase the fervency and urgency with which I seek a connection with you.

Conclusion

When life confuses us, we don't always need immediate answers. Sometimes, the first step is to acknowledge our confusion, become humble enough to seek guidance, and remain willing to change.

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Welcome to the Article #7 in the Inner Journey - Reflections Within - Series !

In my previous post Inner Journey - Reflections Within - Article #6, I shared my understandings and reflections from Bhagavad Gita, Chapter 2, Verse 5 .

Continuing this journey, in this post, I will be sharing my understandings and reflections from Chapter 2, Verse 6.

Let’s get started !

The commentaries and practical relevance shared here are not my original work. They are the result of studying and learning from various sources, which I have consolidated and presented based on my current understanding. This article is therefore a reflection of my learning journey rather than an authoritative interpretation.

Verse 6

न चैतद्विद्म: कतरन्नो गरीयो
यद्वा जयेम यदि वा नो जयेयु: ।
यानेव हत्वा न जिजीविषाम
स्तेऽवस्थिता: प्रमुखे धार्तराष्ट्रा: ॥ 6॥

Meaning

Arjuna says : Nor do I know which is better - conquering them or being conquered by them. We would certainly never want to live if we killed the sons of Dhritarashtra. It would be an empty victory. Yet, they are now standing before us on the battle field.

Dhritarashtra is the paternal uncle of the Pandavas. Sons of Dhritarashtra (Kauravas) are the cousins of Pandavas.

Commentary

Although fighting for a righteous cause is the dharma of every kshatriya, Arjuna is in Dharma Sankat.

Here we see Arjuna move away from the attitude of “I will not fight" to “Should I (or) Should I not fight."

Even if they emerged victorious, it would be an empty victory. Killing their elders, gurus, kith and kin and living in their absence would be another kind of defeat for them.

If the Kauravas emerged victorious, then they would not only have to forego their kingdom but it would also mean defeat of dharma.

This verse shows us how overwhelming attachment and anxiety can disrupt the harmony between mind and reason; where even the sharpest intellect falters making it impossible to act with clarity and purpose.

Modern-Time Relevance

• Confusion is a part of human life,

• Calmness brings clarity.

• Guidance and reflection can help overcome emotional confusion.

Conclusion

In our lives, we may have to make difficult decisions involving people who we respect. Whatever choice we make, we feel that someone will be hurt. We keep thinking about options, but our emotions make it difficult to determine which choice is truly right.
We may reach a point “I don't know what to choose. Either way, I may regret my decision.”

Instead of immediately acting on our emotions, we need to take a step back, calm our mind, seek guidance from someone wise. Gradually, we will be able to see the situation more clearly and make a thoughtful decision.

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Welcome to the Article # 6 of the Inner Journey - Reflections Within - Series !

In my previous post Inner Journey - Reflections Within - Article #5 , I shared my understandings and reflections from Bhagavad Gita, Chapter 2, Verse 4. Continuing this journey, in this post, I will be sharing my understandings and reflections from Chapter 2, Verse 5.

Let’s get started !

The commentaries shared here are not my original work. They are the result of studying and learning from various sources, which I have consolidated and presented based on my current understanding. This article is therefore a reflection of my learning journey rather than an authoritative interpretation.

Verse 5

गुरूनहत्वा हि महानुभावान्
श्रेयो भोक्तुं भैक्ष्यमपीह लोके ।
हत्वार्थकामांस्तु गुरूनिहैव
भुञ्जीय भोगान् रुधिरप्रदिग्धान् ॥ 5॥

Meaning :

Arjuna Says : It is certainly better to not kill our revered teachers. It is better to exist in this world by living on alms rather than taking the lives of great souls.

For the sake of fulfilling our desires of wealth, kingdom and worldly gains, if we kill our gurus who indeed are our superiors, then the fruits of the battle will be tainted by their blood.

Commentary :

Arjuna is not in favor of the war after coming face to face with his elders and teachers in the battle field. But Arjuna is a Kshatriya. It is not his dharma to abandon his responsibilities of a kshatriya i.e., to fight for a righteous cause.

According to scriptures, a teacher who has lost his sense of discrimination of right or wrong or a teacher who has taken sides of unrighteous has lost the respectability of a teacher.

Since this is a war of righteousness, Arjuna need not worry about his hands being tainted with their blood.

Modern-Time Relevance

For me, the relevance of this verse is that dharma should not be abandoned simply because following it becomes emotionally difficult. When our intentions are righteous and our actions are guided by what is right, we should not allow fear, attachment, or personal relationships to prevent us from fulfilling our responsibilities.

In our lives, there may be moments when we have a responsibility to stand up for what is right, even when doing so is uncomfortable or when the people on the other side are people we care about. Avoiding the situation merely because of our emotional attachment may give us temporary comfort, but it may also mean stepping away from our own responsibility.

Example :
Suppose a family member is being treated unfairly in a family situation, but the person responsible is someone you are very close to and respect. You may hesitate to say anything because you don't want to create tension within the family. However, calmly pointing out what is unfair does not mean that you disrespect that person. It means that what is right is stronger than your personal attachment.

Conclusion

For me, this verse is a reminder that fulfilling our responsibilities does not always mean choosing what is comfortable. Sometimes, we may have to step beyond our personal attachments and stand by what is right, even when it is emotionally difficult.

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Welcome to the Article #5 of the Inner Journey - Reflections Within Series !
In my previous post Inner Journey - Reflections Within - Article #4 I shared my understandings and reflections from Bhagavad Gita, Chapter 2, Verse 3. Continuing this journey, in this post, I will be sharing my understandings and reflections from Chapter 2, Verse 4.

With each verse, I find myself looking beyond the words and trying to understand how its teachings relate to my own thoughts, emotions, and experiences in everyday life.

Verse 4 brings us to another dimension of Arjuna’s inner conflict, where his respect and emotional attachment towards those standing before him make the situation even more difficult.

Let’s get started !

The commentaries and practical relevance shared here are not my original work. They are the result of studying and learning from various sources, which I have consolidated and presented based on my current understanding. This article is therefore a reflection of my learning journey rather than an authoritative interpretation.

Verse 4

अर्जुन उवाच ।
कथं भीष्ममहं सङ्ख्ये द्रोणं च मधुसूदन ।
इषुभि: प्रतियोत्स्यामि पूजार्हावरिसूदन ॥ 4॥

Meaning

Arjuna says : O killer of enemies, O killer of Madhu, how can I counter attack with arrows in the battlefield i.e., how can I fight against my revered grand uncle Bhisma (our family patriarch) and our revered Master or Teacher Drona, who are worthy of my worship or who deserve reverence/respect.

Commentary

Arjuna is facing a situational problem. He is stuck in “dharma sankat"; a conflict of dharma. If Arjuna goes forward and fights, the outcome will be very bad. Many revered elders and kith and kin will be killed. But if he choses not to fight, the outcome will be even worse. The kingdom will be ruled over by unrighteous people. This is a situation where both the outcomes will be horrible.

Arjuna’s dilemma is how can he counter attack respectable superiors who are always to be revered.

Here Arjuna addresses Krishan as slayer of the demon Madhu and “slayer of foes” hinting that it is easy to slay evil people but difficult to slay our own people.

This verse highlights the human struggle between personal relationship and responsibilities; the inner conflict between duty and emotion.

Arjuna struggles because he values and respects relationships and elders but his duty as a warrior demands action. His emotions overpower his clarity.

Krishna understands Arjuna’s emotional dilemma and he doesn’t overlook it. He addresses it in future verses.

Modern-Time Relevance

In today’s world, we often find ourselves in situations where we have to make difficult decisions involving people we respect, care about, or look up to. At such moments, our emotions can make it difficult to see the situation objectively.

Verse 4 reminds me that conflict can become especially difficult when the people involved are close to us or when we deeply respect them.

We can experience something similar in our everyday lives, where we have to set boundaries with a loved one or choose what is right even when it may disappoint someone close to us. In such situations, our respect and emotional attachment can sometimes make us hesitate.

The verse made me reflect that respecting someone does not necessarily mean agreeing with everything they do, and standing for what we believe is right does not mean that we have to lose respect for the person.

The challenge is to separate our emotions and personal relationships from the decision itself and act with clarity.

For me, the modern relevance of this verse lies in learning how to handle such conflicts with respect, emotional maturity, and clarity of thought, rather than allowing attachment or fear to completely guide my decisions.

Conclusion

This verse reminds us that compassion and respect are indeed valuable qualities, but difficult situations require wisdom, clarity and understanding of higher responsibility. It teaches the importance of balancing emotions with Dharma and righteous action.

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Welcome to Article #4 on the Inner Journey - Reflections Within - Series !

In my previous post Inner Journey - Reflections Within - Article #3, I shared my understandings and reflections from Bhagavad Gita, Chapter 2, Verse 2. Continuing this journey, in this post, I would like to share what I understood and reflected upon from Verse 3.

In this article, I share the shloka, its direct meaning, insights from various commentaries, and it’s relevance to our everyday lives.

As I continue reading the Gita, I am slowly beginning to see how each verse offers not just spiritual wisdom, but also an opportunity to look within and reflect on my own thoughts, emotions, and actions.

Let’s get started !

The commentaries and practical relevance shared here are not my original work. They are the result of studying and learning from various sources, which I have consolidated and fine-tuned based on my present understanding. This article is therefore a reflection of my learning journey rather than an authoritative interpretation.

Verse 3

क्लैब्यं मा स्म गम: पार्थ नैतत्त्वय्युपपद्यते ।
क्षुद्रं हृदयदौर्बल्यं त्यक्त्वोत्तिष्ठ परन्तप ॥ 3॥

Meaning :

Oh Paratha (Arjuna), do not yield to this unmanliness or impotence. It does not befit you. Give up such petty weakness of heart (emotions). Arise Oh chastiser of enemies.

Commentary :

Arjuna is a mighty warrior. Krishna’s emotional support to Arjuna has to be appropriate for his mighty stature. Hence Krishna uses strong, harsh words.

Arjuna is the son of Kshatriya. If he declines to fight, he remains a Kshatriya by name only. Such Kshatriyas are unworthy sons of their father.

The reason for addressing Arjuna as Parth : Pritha is another name of Kunti. By referring Arjuna as Parth, he reminds Arjuna that he is the son of a Kshatriya queen with great qualities of a warrior. Before the war, Krishna meets Kunti and asks her if there is any message that she would like to pass on to her sons. Kunti replies that she wants her sons to know that this is the moment for which a Kshatriya is born; that time is upon us.

Krishna reminds Arjuna that his behavior is not befitting the son of the great queen.

Arjuna is also referred to as parantapa. Arjuna has defeated several external enemies. He is now confronted with internal enemies like sorrow, compassion, delusion etc. The lord inspires Arjuna to conquer them, as he conquered other enemies.

Arjuna was the most intimate friend of Krishna. Krishna was directly guiding him on his chariot. If Arjuna abandoned the battle, he would be committing an infamous act. Hence Krishna uses strong words.

Another example to show Arjuna’s plight : When we see a new born calf struggling to get up, we know with a little help it can stand on its own feet. But if a calf doesn’t make any effort, the farmer knows that it will not survive. Arjuna is struggling with his emotions, with what is right and wrong. Krishna knows that with his guidance, Arjuna will ultimately fight for the cause of righteousness. But Duryodhana on the other hand refuses to take Krishna’s advice and hence this leads to his downfall. Hence Krishna urges Arjuna to listen to him.

When Krishna uses the word “cast away/ give up" he is emphasizing that it is not something external that has come upon him, rather it is something that he is holding onto, rationalizing it.

In chapter 1, Arjuna puts down his weapons and sits down in his chariot. Now when Krishna tells Arjuna to rise, he means both literally and metaphorically i.e., rise in spirit and rise and get ready to fight.

Relevance in Modern Times

This verse teaches us that :

• Fear and weakness should never define our true identity.

• Temporary emotions should not control our decisions.

  For example, when anger arises, it only makes us angry if we accept it. Similarly negative emotions like greed, fear, lust etc start to control us when we let them gain a hold on us. Worrisome thoughts may enter our minds, but if we do not dwell on them, they will pass. If we focus our attention elsewhere, these troubling thoughts will come and go, much like many other thoughts that surface in our minds without affecting us. They stay at the periphery of our awareness and eventually fade away.

• True strength comes from overcoming fear and acting with determination.

• Courage leads to growth and transformation.

Conclusion

Verse 3 made me reflect on how easily we can become overwhelmed by our own thoughts, fears, and moments of self-doubt. Sometimes, what we need is not to escape from a difficult situation, but to find the inner strength to face it with clarity and courage.

For me, this verse is a gentle reminder that growth begins when we stop allowing our temporary emotions to define us. The journey of understanding the self is not about becoming free from challenges, but about learning how to respond to them with greater awareness and strength.

As I continue with the next verses, I hope to keep reflecting not only on what the Gita teaches, but also on how these teachings can find a place in my everyday life.

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Welcome to the new post of DFT Basics - Series !

In this post, we can explore the concept of coverage, coverage analysis and coverage improvement techniques.

I would recommend that you read Automatic Test Pattern Generation, where we have discussed the basics fault simulation, to better understand this post.

Let’s get started !

Coverage : It is a measure of percentage of faults that can be detected by the generated test patterns out of the total no. of faults that could exist in a circuit.

For example,

If our coverage is 98%, it means 98% of the faulty behaviors which is modelled /mimicked by the the tool (faults) is detected. It implies that if any of those faulty behaviors as modelled/mimicked by the tool occurs after manufacturing due to the presence of a defect, then it will get detected with our test pattern.

Role of DFT Engineers :

Coverage Analysis : in the above example, we need to see why the tool was not able to find a pattern in order to detect those remaining 2% of faults.

Steps for performing coverage analysis in Tessent tools :

• write down the faults into a file

  write_faults <file_name> -class <class_name>

  For example, write_faults AU_PC.txt -class AU.PC → it will generate a fault report for pin-constraint class of faults

• Select any fault from the file and analyze the fault

  analyze_fault <pin_hierarchy> -stuck_at 0/1 -D

  -D → to open in the schematic
  

Coverage Improvement : We need to do something (For example, test point insertion) so that the tool will be able to find a pattern in order to detect the remaining 2% of the faults.

Coverage Drop due to pin-constraint

These are the faults that are uncontrollable (as depicted in pink in the below diagram) or that cannot be propagated to an observation point (as depicted in blue in the below diagram), in the presence of a constraint value. That is, because the tool cannot toggle the pin, the tool cannot test the fanout.

For example :

• The above mux is added to resolve the Scan DRCs.

• The selection line of mux is connected to TM signal.

  < < TM = 0 in functional mode and 1 in DFT mode > >

• A pin constraint of 1 is added to the TM signal (add_pin_constraint c1 TM)

• Therefore, the selection line of the mux will always be 1 in DFT mode.

• Therefore, the A input of mux (0th input of mux) is never selected in DFT mode. So the value of the logics connected to the A input of mux (0th input of mux) can’t be propagated to an observation point. Hence, SA0 and SA1 on those logics can’t be detected.
  

Coverage improvement :

Add an observation point to cover those faults.

Observation point is a scan flop and it will be incorporated into our scan chain

Coverage Drop due to Black Box

These are the faults that are untestable to due a black box, which includes the faults that need to be propagated through the black box to reach an observation point (as depicted in blue in the below figure), as well as faults whose control or observation requires values from the output(s) of a black box (as depicted in pink in the below figure).

Coverage Improvement :

Bypass the Black box to improve the coverage

Coverage Drop due to insufficient Sequential Depth

Sequential depth refers to the number of clock cycles required to capture the fault.

Increasing sequential depth means increasing the no. of capture pulses.

For example,

Consider that there is a non-scan flop between 2 scan flops.

Some flops the designer would have specified that, they should not be scanned.

For example, the flops that hold some encryption data. The designer will specify to not scan them, because if it’s scanned then the encryption data that is loaded on the flops will get shifted out. But it is a protected data and should not be shifted out.

Solution : Increase the sequential depth

Command to improve the coverage (to increase the sequential depth) :

set_pattern_type -sequential <depth> → Command is specific to the Tessent Tools

For example, set_pattern_type -sequential 2 → enables the tool to create clock sequential patterns with up to 2 clock pulses between scan loads.

Coverage Drop due to Mask POs

Firstly, we will explore why POs are masked during ATPG?

After manufacturing, when chips are tested on the ATE, we will be connecting only edt_channel_in and edt_channel_out. We will not be connecting the PI and PO to the tester, so that we can test more no. of chips at a time.

For example,

As we don’t connect the PO to the tester, we will mask the PO during ATPG.

Command → add_output_masks - all

Mask PO class of faults : These are the faults that exist in the fan-in cone of masked POs (the value at PO will not be compared with the expected value) and have no path to other observation points.
For example,

Coverage Improvement : Add an observation point

Coverage Drop due to Undetected (UD) class faults

There is an automatic flow in Tessent tools to add control and observation points to improve the coverage due to Undetected (UD) class of faults.

Coverage Improvement Commands :

• set_test_point_analysis_options - total_number <specify the number>

  Specifies the maximum no. of test-points to be inserted

• analyze_test_points

  Specifies the test-point analysis and generates a list of test-points to be inserted by the tool.

• insert_test_logic

  Inserts the test-points into our design

Coverage Drop due to EDT Abort class of faults

EAB faults : If our design's chain : channel ratio (compression ratio) is insufficient to detect the fault.

Coverage Improvement :

We can use analyze_compression command to determine the compression ratio of a particular project.

Coverage Drop to insufficient Abort limit

What is Abort Limit ?

The abort limit in Tessent ATPG refers to the maximum number of iterations that the tool will attempt before terminating the fault simulation process.

The purpose of the abort limit is to prevent the tool from spending an excessive amount of time searching for a solution that may not exist or may be impractical to find.

ATPG Abort class of faults :

These are faults that are undetected because the tool reached its abort limit.

Coverage Improvement :

You can raise the abort limit to increase coverage using the set_abort_limit command.

Coverage Drop due to memories

ATPG tool will consider the output of memories to be X. So X will be propagated to the downstream logic.

Coverage Improvement :

Bypass the memory to stop X propagation.

< < The selection line of mux (mem_bypass_en) = 0 during MBIST or functional mode and 1 during other times > >

The .tcd_mem_lib file is an input of MBIST run. In the .tcd_mem_lib file, if Transparent Mode option is given as SyncMux, the tool will automatically add the above memory bypassing logic along with MBIST related logics.

Conclusion :

In this article, we have explored some of the reasons for getting coverage drop and the ways to improve the coverage.

References :

Tessent User Manual

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Welcome to the Article #3 on the Inner Journey - Reflections Within - Series !

In the previous article Inner Journey - Reflections Within - Article #2, I shared my understanding and reflections on Chapter 2, Verse 1. Continuing this journey, in this article , we can explore Chapter 2, Verse 2 through the shloka, its direct meaning, commentaries, and its relevance to our everyday lives. Rather than offering a scholarly interpretation, I will be sharing the reflections and insights that I have learnt during my study, along with how I find them relevant to our everyday lives.

Let’s get started !

The commentaries and relevance discussed in this article are not my original interpretations. They have been consolidated and presented based on my study of various books, articles and lectures. I have tried to bring together these learnings in a simple and structured way that reflects my current understanding.

Verse 2

श्रीभगवानुवाच ।
कुतस्त्वा कश्मलमिदं विषमे समुपस्थितम् ।
अनार्यजुष्टमस्वर्ग्यमकीर्तिकरमर्जुन ॥ 2॥

Meaning :

Krishna is referred to as Bhagavan / Brahman - the impersonal all-pervasive consciousness. He is the supreme cause of all causes.

The term Bhagavan refers to one who possesses these six opulence - wealth, beauty, fame, knowledge, strength and renunciation. While ordinary people might possess some of these opulence partially, Krishna possesses all six completely, confirming his divine status.

Lord Krishna uses strong words and admonishes Arjuna and tries to motivate him to fight.

He says, “from where have these impurities come upon you at this hour of crisis?" They do not befit a noble person (a Kshatriya, an Aryan) like you. Such thoughts are not holy and they will not lead you to heaven. It will be the cause of your infamy.”

Commentary :

Arjuna is incapacitated by his emotions. This is a sign of humanity, not weakness. Krishna is addressing Arjuna’s “apparent” weakness.

Arjuna is a Kshatriya. In the presence of Lord Krishna, Arjuna’s lamentation for his kinsmen is certainly unbecoming.

The word “Aryan” is applicable to the class of people who follow dharma, ethics. They excel in nobility and their life is enlightened. The Aryan is a person who is not tempted into doing the wrong things nor is scared of doing the right thing. It is either temptation or fear which makes a man do wrong things. An Aryan is one who is above temptation.

People who are captivated by the external features of this material world do not know the meaning of liberation. Such people are called non-Aryans.

Arjuna is a Kshatriya. He is deviating from his prescribed duties by declining to fight. This act can be considered as cowardice and sinful. It does not befit Aryans. Such deviation from duty does not help one in the progress of spiritual life to higher planes nor does it give the opportunity to become famous.

Krishna doesn’t approve of the “so-called compassion” of Arjuna towards his kinsmen.

Modern-Day Relevance

It is easy to be moral and strong when life is smooth but your true alignment with Dharma is tested only during crisis.

Dharma - the righteous way of living, a code of proper conduct confirming to one’s moral responsibilities or duties.

For example, the dharma of a farmer differs from the dharma of a soldier.

Certain desires, thoughts or feelings may unexpectedly arise within us out of nowhere. If such impulses surface, it is crucial to recognize - This is not who I am, This is not who I want to be. A moment of clarity arises. With this understanding, we gain strength to reject the particular thought, refusing to let it define us. This conscious choice reaffirms our commitment to living in alignment with our values.

Often life distracts us, diverts us not through sudden, sharp turns but through subtle, gradual shifts which we may not even notice. This path may seem harmless at first but before we are even aware of it, it takes us far from our original goal.

Just as Krishna points out to Arjuna and reminds him that such behavior doesn’t befit him, if someone points out that this is not what you were meant to do, it can awaken our awareness and with that recognition, we can check ourselves and align ourselves with our true nature.

Conclusion

Every verse of the Bhagavad Gita seems to open another door for reflection. In the next article, we will continue with the next verse, taking one more step on this inner journey.

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Welcome to the new post in the Have you ever wondered? - series !
In DFT Basics : Article #12, we had explored the working of Decompressor. We had seen that, the output of LFSR logic has diagonal relationship between adjacent bit streams. Because of this, the tool will not be able to generate all possible combinations of patterns to detect all the faults. In order to introduce more randomness between the bit streams, output of LFSR will be given to the phase shifter, which is implemented by XOR network. In the presence of phase shifter, the diagonal relationship no longer exists. More randomness helps in increasing the fault coverage. Phase shifter also helps supporting more scan chains.

Have you ever wondered how the phase shifter logic is implemented? Have you ever wondered why phase shifter is implemented using XOR gates?
We will explore it in this blog.

Let’s get started !

We will use the below example in this blog.

Image Source : VLSI tutorials - Showing the working of a phase shifter

• In the above figure, the period of LFSR is 15 (as the sequence repeats every 15 cycles).

• At the output of phase shifter, if we want 5 different outputs (as shown in the above figure) :
  15 positions, 5 outputs

  => 15/5 = 3

  Therefore, in the above figure, we have chosen phases 0, 3, 6, 9, 12

  ---

Q3 phase shift by 0

Figure : Q3 phase shifted by 0

It is exactly the same as the original Q3, as marked in the above figure.

Q3 phase shift by 3

The above figure depicts how to derive Q3 phase shifted by 3.

Figure : Q3 phase shifted by 3

Q3 phase shifted by 6

The above figure depicts how to derive Q3 phase shifted by 6.

Figure : Q3 phase shifted by 6

Similarly Q3 phase shift by 9 and 12 have to be derived.

How to arrive at the XOR network ?

XOR Network

Similarly we need to derive it for the other outputs of phase shifter (phase shift by 6, 9 and 12) to form the complete phase shifter logic.

References:

VLSI Tutorials

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Welcome to the Article #2 of the Inner Journey - Reflections Within - Series !

In the previous article Inner Journey - Reflections Within Article #1, we began with the traditional prayer that invokes harmony between the teacher and the student . With that foundation, we now begin our journey into the teachings of the Bhagavad Gita.
In this article, we explore Chapter 2, Verse 1 from my current understanding. Rather than offering a scholarly interpretation, I will be sharing the reflections and insights that I learnt during my study, along with how I find them relevant to our everyday lives.
Let’s get started !

Note :
The explanations, commentaries, and practical insights presented here have been compiled from multiple authentic sources that I have studied over time. I have attempted to consolidate, and present them based on my current understanding.

The Bhagavad Gita - Chapter 2 - Sankya Yoga

Chapter 2 of the Bhagavad Gita contains 72 verses. This chapter can be considered as the essence of teachings of Bhagavad Gita.
It is called the Sankya Yoga because it introduces the core philosophy of Gita i.e., Viveka - The discrimination of real (satya - eternal and unchanging) and unreal (things that are subject to change). The word Sankya literally means analysis. In the context of Gita, it refers to the discernment between the eternal soul (Atman) and the temporary body and mind; between true knowledge and ignorance. It lays the foundations for teachings on action (Karma Yoga), meditation (Dhyana Yoga) and wisdom (Jnana Yoga).

Chapter 2 is one of the most important chapters of the Gita because

• It shifts Arjuna’s perspective from fear and confusion to spiritual inquiry.

• Introduces the eternal nature of the self beyond the body.

• Explains Karma Yoga - Selfless action.

• Describes the ideal state of balanced wisdom.

• Shows how detachment and duty leads to inner peace and freedom.

Verse 1 :

सञ्जय उवाच ।
तं तथा कृपयाविष्टमश्रुपूर्णाकुलेक्षणम् ।
विषीदन्तमिदं वाक्यमुवाच मधुसूदन: ॥ 1॥

Meaning :

Sanjaya says these words.

< < Sanjay is the advisor of the blind king Dhritharashtra (father of Kauravas) > >

Sanjay is blessed by Sage Vyasa with a divine eye. Sanjaya describes Arjuna’s intense emotional and psychological breakdown to king Dhritharashtra.

Seeing Arjuna overwhelmed by compassion, seeing him disturbed and his eyes filled with tears, Madhusudana (Krishna) spoke these words to the lamenting Arjuna (Verse 2 will cover these words).

Commentary :

In the first chapter, we can see that Arjuna is in an emotional distress. His intellect has been hijacked by his emotions. Only intellect can discern dharma.

This war is a dharma yudha; a righteous war. Not fighting this war will lead to worse consequences.

Dhritharashtra is the blind king. One can see the symbolism. He is not only physically blind but he is blind to dharma also. He doesn’t impart proper guidance to his son Duryodhana.

If the war is not fought, the kingdom will not prosper under the rule of the blind king and his unrighteous son.

Arjuna is in emotional distress. It has led to his emotional paralysis and emotional meltdown. He is facing a conflict between the head (intellect) and heart (emotions).

Arjuna is a Kshatriya. He was the world’s greatest archer, highly intelligent and morally upright. Yet when faced with personal crisis, his clarity dissolved into severe anxiety. This conduct was not expected from him.
Compassion, lamentation, tears are all signs of ignorance of real self.

Relevance of this verse in modern times

Sri Krishna’s teachings are eternal and relevant for all times.

Each one of us have to fight some battle or other in our daily life. We all face challenges like ill-health, bad financial situation, difficult job, people, loneliness etc.

Mental health struggles, anxiety, decision paralysis can happen to the strongest of us. Being overwhelmed by life’s battles does not make you weak; it simply means you are a human and currently out of alignment.

This verse is the dark before dawn. It captures a moment of intense human suffering right before the descent of ultimate cosmic wisdom.

It reassures us that no matter how clouded our vision is today, when we stand alongside truth and seek guidance, clarity is bound to follow.

Conclusion

In reply to Arjuna’s lamentation, Sri Krishna uses sharp words, harsh words; literally hammer blows. It is a sort of reality check to Arjuna. This can be seen in the following verses.

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Welcome to Inner Journey – Reflections Within Series !

This series is a collection of my personal learnings and reflections from the Bhagavad Gita, one step at a time.

I'm neither a teacher nor an authority. I am just a fellow seeker sharing what I learn along the way.

As my understanding evolves, so will these reflections. I hope these articles inspire thoughtful inquiry and perhaps encourage you to begin—or continue—your own inner journey.

Let’s get started !

Every meaningful journey begins with a prayer. As I begin sharing my learnings and reflections through this series, it feels only natural to start with a timeless invocation that has been recited by seekers and teachers for generations. More than just words, this prayer beautifully expresses the attitude with which knowledge is to be sought—with humility, sincerity, togetherness, and peace.

In Article #1 on this series, let us begin with a beautiful Shanti Mantra :

ॐ सह नाववतु ।
सह नौ भुनक्तु ।
सह वीर्यं करवावहै ।
तेजस्वि नावधीतमस्तु मा विद्विषावहै ।
ॐ शान्तिः शान्तिः शान्तिः ॥

Meaning of each word

• ॐ - The symbol of parabrahman. The one who protects, the one who sustains everything.

• सह - Together (The teacher and the student)

• नाववतु - नौ (we two) + अव (to move, to protect) + अवतु (may we move)

• भुनक्तु - May we relish/enjoy

• वीर्यं - Strength, power, vigor

• करवावहै - May we perform

• तेजस्वि - Filled with Tejas, Brilliance

• नावधीतमस्तु - नौ + अधीतम् + अस्तु - our + study + may it be

• मा विद्विषावहै - May it not + hostility

Meaning of the Shloka

• May the lord, who is the source of all blessings, the source of all knowledge, protect both of us (the student and the teacher).

• May he nourish both of us with this knowledge.

• May the lord, indeed, ignoring all my omissions, bless and nourish us both.

• May we surrender to the one because of whom this knowledge can be understood.

• May both of us make effort for the capacity of knowledge.

  < < The teacher should have the capacity to impart knowledge, the student should have the capacity to gain knowledge. The teacher has to make an effort to explain clearly, clarify any doubts. On the part of student, capacity should be in the form of commitment, power of retention and recollection. The teacher and the student are at the same level > >

• May what is studied be brilliantly clear, meaningful, free from vagueness.

• May we not be subject to any kind of misunderstanding so that this communication is complete.

• Let there be freedom from 3 obstacles - ॐ शान्तिः शान्तिः शान्तिः
  Adidaivika - Obstacles from forces over which we have no control. For example, Natural Calamities.

  Adibhautika - Obstacles arounds us. Social, domestic, political problems.

  Aadhyathmika - Problems centered on self (physical, physiological, mental)

  I pray that the 3 capacities - physical (deha), physiological (prana) and mental (mana) will be available to me in a manner that is conducive to my pursuit of this knowledge.

  I pray for the freedom from these three obstacles.

These reflections are simply my current understanding as a fellow seeker.

In the next article, I’ll begin sharing what I’ve learned from Chapter 2 of the Bhagavad Gita, one verse and one reflection at a time.

Thank you for being a part of this journey.

References

• Bhagavad Gita

• Commentaries and lectures by various teachers

• Videos from YouTube

This article is a reflection of my personal understanding, inspired by the above sources.

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As modern System-on-Chip (SoC) designs continue to integrate multiple IPs and cores, managing scan test access becomes increasingly challenging. Traditional scan architectures either require a large number of chip-level scan pins to test multiple cores in parallel or force cores to share pins, increasing the overall test time. To address these limitations, Streaming Scan Network (SSN) provides an efficient packet-based scan transport architecture that enables high-bandwidth scan data delivery using fewer external scan channels.

In this blog, we will understand the motivation behind SSN, and how it enables efficient concurrent testing of multiple cores.

Let’s get started !

Let’s explore an example :

• Core A needs 5 scan channels

• Core B needs 4 scan channels

Case1 : Traditional Pin-sharing technique

• The same top-level scan pins are shared between the two cores.

• First test Core A using 5 channels.

• Then switch to test Core B using 4 channels.

• Only 5 top-level input pins (and corresponding outputs) are required.

• Disadvantage: Test time is the sum of both cores since they are tested one after another.

Case2 : Parallel testing : Both cores must receive scan data simultaneously.

• Required channels = 5 + 4 = 9.

• Therefore, you need 9 inputs and 9 outputs at the top level.

• Advantage: Lower test time.

• Disadvantage: More chip-level scan pins are required

What if only 8 top-level scan channels are available?

This is exactly where Streaming Scan Network (SSN) becomes useful.

Streaming Scan Network

• SSN is a bus-based scan data distribution architecture.

• Each core typically contains one Streaming Scan Host (SSH) node (light blue box).

• The SSH drives local scan resources with data delivered on the SSN bus.

Image Source : Tessent Streaming Scan Network

How SSN works

• In our example, CoreA has 5 EDT channels and CoreB has 4 EDT channels. In order to parallelly test them, we require 9 inputs and 9 outputs at the top level. But only 8 top level scan channels are available.

• With SSN, the packet size is set to nine bits independent of the SSN bus width, which is eight bits in this example.
  < < If we want to test CoreA and CoreB at the same time, we require 9 bits of data. The amount of data required to perform shift cycle for all the cores that test in parallel is called packet > >

  

  Image Source : Tessent Streaming Scan Network

• The first five bits of every nine-bit packet are programmed to belong to block A, and the next four bits of every packet are programmed to belong to block B.

• As soon as block A extracts 5 bits from the bus, it performs one internal shift operation. Likewise for block B, every time it accumulates 4 bits.

• In this example with 9-bit packets and an 8-bit bus, the blocks shift approximately every bus/ tester clock cycle. Occasionally, a block may omit shifting in a given cycle because it has to wait to acquire all the bits it needs for one shift cycle.

• In the first tester cycle, the tester sends AI00 AI01 AI02 AI03 AI04 BI00 BI01 BI02 on the SSN bus.

• Now coreA’s SSH (Streaming Scan Host) has received 5 bits. So It will apply those bits to the coreA’s decompressor. CoreA’s decompressor will later decompress that data and apply a unique sequence into each of the internal chains of CoreA (1st bit of pattern 1 is applied).

  But CoreB has only received 3 bits. So it’s SSH will only store the bits.

• In the second tester cycle, the tester sends BI03, AI10, AI11, AI12, AI13, AI14, BI10, BI11 on the SSN bus.

• Now coreB’s SSH has received all the 4 bits (BI00 to 02 in the first tester cycle and BI03 in this tester cycle). So it will apply those bits to the coreB’s decompressor. CoreB’s decompressor will later decompress that data and apply a unique sequence into each of the internal chains of CoreB (1st bit of pattern 1 is applied to CoreB).

  CoreA’s SSH has also received the next 5 bits (AI10, AI11, AI12, AI13, AI14). So It will apply those bits to the coreA’s decompressor. CoreA’s decompressor will later decompress that data and apply a unique sequence into each of the internal chains of CoreA (2nd bit of pattern 1 is applied to CoreA).

  CoreB has received only 2 bits (BI10, BI11) of the next shift. So it will just be stored in the SSH of coreB.

• Capture involves events generated by the SSH such as de-asserting scan_enable, applying capture clocks through an OCC, and re-asserting scan_ enable in preparation for the next scan operation.

• Typically, the same time slots of the packet that carry scan-in data to an SSH node also carry scan-out data from that node. As block A reads the first 5 bits of every packet, it replaces them with 5 bits scanned out (with slight latency).

In this blog, we explored the motivation behind Streaming Scan Network (SSN), understood how it overcomes the limitations of traditional pin-sharing techniques, and saw how scan data is efficiently streamed to multiple cores using the available tester bandwidth. SSN is an important advancement in modern DFT that enables scalable testing of complex SoCs while balancing pin count, bandwidth, and test time.

Disclaimer: I am currently learning Streaming Scan Network (SSN), and this article reflects my understanding and learnings based on the resources I have studied. While I have made every effort to ensure the information is accurate, I cannot guarantee that every explanation is 100% correct. If you notice any inaccuracies or have suggestions for improvement, I would sincerely appreciate your feedback. Learning is a continuous process, and your insights are always welcome.

References :

1. Tessent Streaming Scan Network: No-compromise packetitized test

2. Tessent Streaming Scan Network (SSN): No-compromise DFT by Peter Orlando, Siemens EDA (You tube video)

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Welcome to the first post in the MBIST series. In this article, we explore the fundamentals of MBIST, with a focus on building strong conceptual understanding.

Below is a list of topics covered in this post:

1. Memory fault models

2. A sample memory test algorithm

3. Illustrations to explain how memories are tested using generalized algorithms

4. Common questions that freshers typically have when encountering MBIST for the first time.

MEMORY FAULT MODEL

SINGLE CELL FAULT MODEL

1. Stuck-At Fault (SAF)

• a cell is always 0, SA0

• a cell is always 1, SA1

2. Transition Fault :

   a cell fails to undergo a 0 ->1 transition or 1-> 0 transition when it is written.

DOUBLE CELL FAULT MODEL

Coupling Fault(CF):

Victim cell is affected by Aggressor cell. The value in the aggressor cell can affect the value in the victim cell

.

Types of coupling fault :

1.State coupling fault

2.Inversion coupling fault

3.Idempotent coupling fault

1.State Coupling Fault (CFst)

if aggressor cell is in given state, victim cell is forced to 0 or 1

4 TYPES :

• When aggressor cell is in logic 0, then victim cell will be stuck at logic 1.

Similarly the other types of State Coupling Faults :

• When aggressor cell is in logic 0, then victim cell will be stuck at logic 0.

• When aggressor cell is in logic 1, then victim cell will be stuck at logic 0.

• When aggressor cell is in logic 1, then victim cell will be stuck at logic 1.

2. Inversion Coupling Fault (CFin)

   if aggressor cell rise/fall, victim cell is complemented.

2 TYPES :

• If there is a rise transition in aggressor cell, no matter which state the victim is in, victim cell will be complemented.

  

  

  Similarly,

• If there is a fall transition in aggressor cell, no matter which state the victim is in, victim cell will be complemented.

3. Idempotent Coupling Fault (CFid)

   if aggressor cell rise/fall, victim cell is forced to 0 or 1.

4 TYPES :

• When aggressor cell is having a rise transition, then victim cell will be forced to logic 1.

Similarly the other types of Idempotent Coupling Faults :

• When aggressor cell is having a rise transition, then victim cell will be forced to logic 0.

• When aggressor cell is having a fall transition, then victim cell will be forced to logic 1.

• When aggressor cell is having a fall transition, then victim cell will be forced logic 0.

Address-Decoder Fault(AF)

Four faulty behavior:

• Given a certain address, no cell will be accessed

• A certain cell is never accessed by any address

• A certain cell can be accessed by multiple addresses

• Given a certain address, multiple cells are accessed (2 types : AND type and OR type)

  

  ---

  In the previous section, we explored various memory fault models. In the next section, let’s explore how memories are tested using generalized algorithms.

  ---

  MEMORY TEST ALGORITHMS

• A Test algorithm is a finite sequence of test elements

• A test element contains a number of :

  1. Memory Operations : Read or Write

  2. Data pattern : Zero or One

  3. Address sequence : Ascending or Descending

Let’s explore a Memory Test Algorithm :

We have explored the sequence of an algorithm. Now let’s explore how this algorithm covers various memory faults.

• This algorithm covers all the SA faults, since we are reading 0 and 1 from all the cells.

• This algorithm covers all the Transition faults, since

  

• This algorithm covers all the Address decoder faults

  

  Similarly,

  

• This algorithm covers all the inversion coupling faults

  

Illustration 1 :

Illustration 2 :

Illustration 3:

Illustration 4 :

In the previous sections, we explored the various memory fault models and how memories are tested using generalized algorithms.

In the next section, we will explore the most common questions that freshers typically have when encountering MBIST for the first time.

Common questions that freshers typically have when encountering MBIST for the first time :

Q1 : Why memories are tested using generalized algorithms?

Ans : In regular designs, the combo logic between the 2 flops will vary. So we can’t write a generalized algorithm to test the combo logic. So in order to test the combo logic, we write appropriate patterns.

But memories will have a symmetric tightly packed structure. Only its size will vary from one memory to other memory. So we can use generalized algorithm to test the memory.

Q2 : Why aren’t we working on coverage analysis and improvement in MBIST?

Ans : For memories, we have generalized algorithms. In various tool user manuals, we will get information of which algorithm will be able to cover which faults in memories. If it is mentioned that, an algorithm covers SA, TF, AF, CF etc.., then it is 100% sure that if any of those faulty behaviors occurs after manufacturing, it will get detected by this algorithm.

Q3 : Why is it called Built-in Self-Test?

Ans : Given an algorithm, the BIST circuitry automatically applies the values onto memory according to the algorithm and the output of memory is also automatically compared with expected value.
(We will explore more on this, while exploring the MBIST architectures)

References :

Lectures from - VLSI testing, National Taiwan University

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Welcome to the second post in the JTAG and IJATG series.

This post, will focus on a detailed comparison between JTAG and IJTAG, highlighting the key advantages of IJTAG (IEEE 1687 standard).

Before proceeding, I recommend reading JTAG and IJTAG Explained : From Basics to Advanced Concepts , where we explored the fundamentals of JTAG and IJTAG and discussed their importance.

Let’s get started !

IEEE 1149.1 standard (JTAG)

IEEE 1149.1 standard (JTAG) (Contd…)

IEEE 1687 standard (IJTAG)

References :
IJTAG VS JTAG VS IEEE 1500 ECT | TECHNICAL TUTORIAL – 2ND EDITION

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In DFT Basics : Article #21, we have explored Transition Delay Fault Model (TDF). We have also explored the ways of detecting Transition faults (LOC and LOS techniques). We have also explored the Pipelined Scan Enable (PSEN) architecture.

Have you ever wondered why we need Path Delay Fault Model (PDF) when we have Transition Delay Fault Model (TDF)?

Let’s explore !

I recommend reading the following two posts before continuing with this article.

DFT Basics : Article #18 - which explains the concept of ATPG and Fault Simulation

DFT Basics : Article #21 - which explains Transition Delay Fault model (TDF)

PATH DELAY FAULT MODEL (PDF)

• Associated with testing at-speed performance of critical path (given by

designer).

• Longest path or the path whose clock frequency is high is usually defined as

critical path because timing violations are more likely to happen.

• Path delay fault model : Path delay of faulty path > clock period

• Path delay fault model is used to detect some manufacturing defect that is

distributed throughout the path (Example : more resistive path)

DIFFERENCE BETWEEN PATH DELAY FAULT MODEL (PDF) AND TRANSITION DELAY FAULT MODEL (TDF)

Let’s try to explore the difference between PDF, TDF and the need of PDF when we have TDF through the below illustrations :

Waveform explanation of the above illustration (1st diagram):

Summarizing the above illustrations :

• We need both PDF and TDF because, with only TDF, we can’t assure that manufacturing defect which is distributed throughout the path will get detected. So we usually do PDF to test critical path.

• Run-time of PDF is high. So we usually do PDF to test the at-speed performance of critical path. To test the other paths, we use TDF.

  ---

  References:

• Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

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Have you ever wondered why we usually add a dedicated wrapper for the PIs (Primary Inputs) that are driving the set/reset ports of a flop?

Let’s explore in this post.

Before reading this post, I recommend going through the following two posts for understanding the Hierarchical Scan concepts:
Scan Wrappers and Hierarchical Scan (Part 1)
Hierarchical Scan Part 2

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In DFT Basics : Article #18, we had explored Fault Simulation and Stuck at Fault Model. In this post, we will explore Transition Delay Fault (TDF) Model.

Let’s get started !

Transition Delay Fault Model

TDF fault model is used to detect that the logic level from 0-1 and 1-0 properly transit within the specific time (time period of fast frequency clock (i.e., functional clock)) or not.

Why fast frequency clock?

Because after manufacturing (i.e., after testing when the chip goes to the customer), only fast frequency clock (i.e., functional clock) will be used. So we need to check whether the rise/fall of signals happens within the time period of fast frequency clock or not.

< < We have explored how the appropriate clock and appropriate no. of clock pulses are propagated in DFT Basics : Article #14 > >

Let’s explore more on TDF using the below example :

Let’s explore the same using a waveform:

The same concept is applied to the other faults and I have arrived at the below tabular column

< < Note : Tool will not write the redundant patterns into the final pattern list > >

Ways to detect TDF faults

• LOC : Launch on Capture (or) Launch off Capture

• LOS : Launch on Shift (or) Launch off Shift

LOC : Launch on Capture (or) Launch off Capture

LOS : Launch on Shift (or) Launch off Shift
In LOS, the launch pulse (i.e., b pulse in our waveforms) will come during SEN=1 and it will be the last shift pulse.

Comparison:

• LOS has slightly more coverage compared to LOC as the tool has more controllability on LOS than LOC.

Explanation:

The tool brings the transition value through shift path in LOS (as depicted with the arrow in the below figure).

Whereas in LOC, the tool has to program the combo logic to get an appropriate value at the output of the combo logic to create the transition (as depicted with an arrow in the below figure).
Suppose the tool is not able to bring the appropriate value at the output of combo logic, then the faults that require that value will not get detected.

• But there is a major limitation in LOS. Controlling SE (timing closure on SE) is extremely difficult. Therefore mostly companies don’t use LOS.

Pipeline Scan Enable (PSEN)

We had explored OCC’s internal architecture in DFT Basics : Article #14.

As per the OCC’s internal architecture, when Scan Enable (SE) = 1, both for SA and TDF, slow frequency clock is propagated.
How while using LOS method, we are able to propagate 1 fast frequency clock (b pulse in our waveforms) during SE = 1 ?

Ans : Using Pipelined Scan Enable (PSEN)

Now let’s explore the PSEN architecture.

Let’s visualize the above diagrams using a waveform :

< < Note : In the above waveform Tcq is the clock to q delay > >

In this post, we had explored Transition Delay Fault (TDF) Model, ways to detect TDF and PSEN architecture.
In the next post, we will explore Path Delay Fault (PDF) Model. We will discuss the necessity of having both PDF and TDF.

Stay Tuned !

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Welcome to the fourth post in this series !
You can also explore DFT Interview : Article #3

In DFT Basics : Article #5 and DFT Basics : Article #6, we have explored the various DRCs which we will encounter during Scan insertion.

In this post, we will explore some of the DRCs which we will encounter during ATPG.

Q: What are the DRC violations which you have encountered during ATPG?

Ans : Some of the DRC violations which we encounter during ATPG are Tracing violations (T rules), D1 violation

1. Tracing Violations :
Some of the tracing violations which we encounter during ATPG are T3, T5, T24 violations (while working with Tessent tools).

• T3 violation : The shift procedure must create a sensitizable path from the scan chain output back to the scan chain input. An improperly sensitized gate in the scan path causes an error condition, which the tool reports as a T3 DRC violation.
  

• T5 violation : During the shift procedure, you must never place an X value on a clock input or an active (X or 1) value on a set or reset input of a memory element in the scan path.

Now let’s explore some practical scenarios which can result in T3 and T5 violations :

Scenario 1:

< < In companies, there will be multiple intermediate releases before the final release > >
Suppose,
During first release :

• Designer has used a set of flops.

• Library file 1 contains the flop models used by the designer.

• Library file 1 is read during Scan and ATPG.

During second release :

• Designer has additionally added few more new flop models.

• Library file 2 contains the additional new flop models used by the designer.

• Both library file 1 and library file 2 is read during Scan.

• During ATPG execution, the old setup was mistakenly used. In this setup (from the first release), only Library File 1 was read. As a result, the newly added flop models were treated as black boxes during ATPG.

In this situation, we will encounter T3 violation.

Solution : Read both the libraries (library file 1 and 2) during ATPG

Scenario 2:

Suppose, during the final release, the designer has manually added a new ICG (Integrated Clock Gating Cell) to reduce the dynamic power (he has done it after scan insertion without informing DFT). In addition, the Test Enable (TE) pin of the ICG was not properly controlled.

In this scenario, we will encounter T3 and T5 violations

Solution :
Connect the TE of ICG to Test Mode [TM] (or)

Connect the TE of TCG to Scan Enable (SE) → This is advantageous

To explore more on ICG, please check DFT Basics : Article #4
To explore more on the fix, please check Answering Curious Minds

Now let’s explore some practical scenarios which can result in T24 violation:
If we have not added a lock up latch for domain mixing, it will result in T24 violation.

To explore more on domain mixing and why a lock up latch is needed during domain mixing, please check DFT Basics : Article #9

2. D1 violation :

   If a Scan clock is pulsed during the load phase, it will result in D1 violation.
   < < Note: In load phase, only edt_clock and edt_update has to be pulsed > >
   

   To explore the reason of why scan clock should not be pulsed during load phase, please check DFT interview : Article #1 (Question 3)
   To explore more on EDT logic, please check my DFT Basics Article 11 to 17.

   

   Now let’s explore some practical scenarios which can result in D1 violation:

   

   < < To understand the ICG structure used in the above figure using a waveform, please check DFT Interview : Article #3 (Question 9 ) > >
   
   Solution :

   

   ---

   References :
   Tessent Scan and ATPG user’s manual

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In my previous blog DFT Basics : Article #19, we had explored Shared and Dedicated Input and Output Wrappers.
In this post, we will explore the various concepts of Hierarchical Scan like Intest, Extest and pattern re-targetting.

Let’s get started !

DESIGN :

CoreA intest

• To test the internal logic of CoreA.

• CoreA’s EDT controls CoreA’s normal SFFs and CoreA’s wrapper flops.
<< For a detailed explanation of EDT logic, please see DFT Basics, Articles 11 to 17 > >

Role of CoreA’s wrapper flops during intest of CoreA :

• Input wrapper chains launch data into the inside logic and output wrapper chains capture data from inside logic (as depicted by arrows in the figure).

  

• During this time, the input sequence will be shifted into the wrapper chains by CoreA EDT.

  < < We have already explored this in detail in DFT Basics : Article #19 > >

Normal Scan Flops will be doing their usual operation (shift, capture, shift-out)
< < We have already explored this in DFT Basics : Article #2> >

CoreA extest

• The testing of interconnections between CoreAs (extest of CoreA) will happen in the CoreB level.

• Last shifted value of CoreA_1’s output side wrapper (blue colour) will be captured into CoreA_2’s input side wrapper (red colour) (As depicted with green lines in the below figure). If there was some defect in the interconnection, then wrong value will be captured.

• During this time (CoreB level), CoreAs will be in extest.
CoreB’s EDT will be shifting the values into CoreA’s wrapper flops.

< < We have already explored this in detail in DFT Basics : Article #19> >

<< For a detailed explanation of EDT logic, please see DFT Basics, Articles 11 to 17 > >

CoreB intest

CoreB extest run

• CoreB extest happens at top level.

• Last shifted value of flop in glue-logic in top will be captured by input side wrapper flop of CoreB (depicted by red arrow in the figure). Similarly last shifted value of CoreB’s output side wrapper will be captured by the flop in glue-logic in Top (depicted by blue arrow in the figure). If there is any defect in the interconnection, then wrong value will be captured.

What is a glue logic?

Pattern re-targetting

• Re-applying already generated CoreA intest patterns from CoreB level instead of generating it again.

  

Note :

After top insertion, CoreA intest patterns will be again re-applied from top level also.

• Why pattern re-targetting ?

  Finally at the tester level, everything has to be applied from top level.

• Why only CoreA intest ?

  CoreA extest (interconnections) are already tested at the CoreB level and patterns are generated from CoreB level.

In this post, we explored various concepts related to Hierarchical Scan. In the next post, we’ll resume our discussion on ATPG coverage.

Stay Tuned !

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In the previous 18 articles of the DFT Basics series, we explored topics such as Scan Insertion, Scan Compression, On-Chip Clock Controller, and ATPG Pattern Generation. In the upcoming posts, we will continue our discussion on ATPG concepts, including coverage analysis and improvement.

In this blog, however, let’s take a brief detour from the ATPG topic and explore the concept of Hierarchical Scan.

Let’s get Started !

Flat Vs Hierarchical Scan

Let’s explore Hierarchical Scan concepts using the below design :

Wrapper Insertion (we will explore w.r.t CoreA level)

Wrapper Chains

Types of Wrapper Cells

< < Note : PI stands for Primary Input (functional input) and PO stands for Primary Output (functional output)> >

Dedicated Wrapper Cell

Shared Wrapper Cell

Let’s explore Shared Input Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
int_ltest_en will be controlled by TDR

Shift Phase :

Capture Phase : (int mode)

< < In int_mode, only the logic internal to the block will be active. Logic external to the block will not be active. It will be X > >

Capture Phase : (ext mode)

Let’s explore Shared Output Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
ext_ltest_en will be controlled by TDR

Shift Phase :

Capture Phase : (int mode)

Capture Phase : (ext mode)

< < In ext_mode, the logic internal to the block will not be active. It will be X > >

Let’s explore Dedicated Input Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
int_ltest_en will be controlled by TDR

Shift Phase :

Capture Phase : (int_mode)

< < In int_mode, only the logic internal to the block will be active. Logic external to the block will not be active. It will be X > >

Capture Phase : (ext_mode)

Let’s explore Dedicated Output Wrapper Cell !

Note :
se is Scan Enable. It will be a top level port.
ext_ltest_en will be controlled by TDR

Shift Phase

Capture Phase : (int mode)

Capture Phase : (ext mode)

< < In ext_mode, the logic internal to the block will not be active. It will be X > >

Let’s summarize the points which we explored above

Wrapper Chains

References :

• Tessent Scan and ATPG user’s manual

• Wrapper Chains by Semicon shorts

• Integrating Wrapped Cores in a Compressed Scan Flow - From Solvnet

In this post, we explored the concept of Scan Wrappers. Building on this foundation, our next post will cover Hierarchical Scan concepts, including INTEST, EXTEST, and pattern re-targeting.

Stay tuned for the next post, coming this Tuesday!

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Welcome to the third post in DFT interview series!
You can also explore DFT Interview : Article #2

Q1 : What is the flow of Scan Insertion in Tessent tools?
Ans :

Setup Phase -

• Reading the input files and library files.

• Elaboration

  - - tool checks if the module definition of all modules is available.

  - - tool checks if all the module instantiations are correct.

• Provide the declarations and constraints.

Analysis Phase -

• DRCs are checked.

< < Design Rule Checks, DRCs, are the set of rules which each flop in the design has to pass in order to be scannable > >

• If there are any DRC violations, go to the setup phase and fix the DRC violations.

• If there are no DRC violations, go to the insertion phase.

Insertion Phase -

• Identify the scan equivalent.

• Replace all the normal flops with scan flops and stitch the scan chains.

• Write out the reports and outputs of scan insertions.

Q2 : Why is scan insertion performed on gate level netlist?

Ans :

In RTL, we don’t have a physical impression of all flops. RTL can also be written with parameters stating multiple flops with single always command. It is difficult to modify such code lines and add mux to it to make it a scan flop.

Q3 : What are the DRC violations you have encountered while performing scan insertions using Tessent tools?

Ans :

S1 violation :

We get S1 violation when

• clock and set/reset declaration is wrong or missing.

• clock or set/reset of a flop is controlled by another flop or any combo logic’s output.

• set/reset of a flop is tied to a fixed value.

S2 violation :

We get S2 violation when

• clock of a flop is tied to a fixed value.

D5 violation : Gives a list of non-scan memory elements

We get D5 violation when

• a flop has S1 or S2 violation.

• a flop’s scan equivalent is not available in the library file.

• if it is a latch.

C6 violation : Clock Data race DRC violation

We get C6 violation when the clock signal goes to the clock pin and D pin of a flop.

E10 violation : Bus contention violation

We have explored all the above DRC violations and their fixes theoretically in Scan DRC (part 1) and in Scan DRC (part 2).

Q4 : What is the auto-fix command in Tessent tool to fix the above DRC violations?

Ans :

set_test_logic command

-clock on : fixes the clock controllability DRC violation

-set on : fixes the set controllability DRC violation

-reset on : fixes the reset controllability DRC violation

-tristate on : fixes the bus contention violation

-C6 on : fixes the C6 violation

Q5 : Consider the below 2 scenarios :

In both the cases, Reset of the flop is tied to a fixed value.

Tessent tool points Scenario 1 as S1 violation. But it doesn’t point Scenario 2 as S1 violation.

Why?

Ans :

Scenario 1 :

• It is an active low reset flop.

• It’s reset pin is tied to Gnd. So the flop’s output goes into a reset state i.e., Q = 0 (since it is an active low reset flop)

• It will affect the state of the flop during shifting (i.e., proper patterns will not get shifted into the scan chains).

• So it is pointed as S1 violation.

Scenario 2 :

• It is an active low reset flop.

• It’s reset pin is tied to Vdd. It is getting it’s off-state value. The circuit operates normally.

• So it is not pointed as S1 violation.

Q6 : Consider the below scenario :

The reset pin of FB is controlled by FA’s Q. But Tessent tool doesn’t point this as S1 violation.
Why?

Ans :

FB is a synchronous reset flop.

We will first explore the difference between Synchronous and Asynchronous Reset flops.

In the case of Asynchronous Reset flop

So we need to fix the S1 violation
< < The explanation of this fix is explored in Scan DRC (part 1) > >

In the case of Synchronous Reset flop,

Q7 : What is C3 violation?
Ans :
When a positive edge triggered flop’s output goes as the D input of a negative edge triggered flop, it is pointed as C3 violation in Tessent Scan tool.

Image Source : Tessent Scan and ATPG User’s Manual

NOTE :

Whenever we have both positive and negative edge triggered flops, for scan path, it will be taken care as discussed in Problems in Edge Mixing :

• While doing scan chain stitching, the tool will try to keep all negative flops at the starting of the scan chain.

• Suppose if the tool is unable to do so, and if there is a positive ff and then negative ff, it will insert Lock up latch.

For C3, the problem is happening at the D path (marked in violet in the above figure). This can cause problem during capture phase. Failure to address this issue can result in simulation mismatches when we verify the test patterns in a timing-based simulator.

Let’s explore the problem with the help of the below waveform :

Image Source : Tessent Scan and ATPG User’s Manual

Solution of C3 violation :

Command :

set_split_capture_cycle on (Note : This command is given in ATPG run)

When set to on, the tool updates simulation data between clock edges. This “split capture cycling” of data allows the tool to determine correct capture values for trailing edge and level-sensitive state elements, even in the presence of C3 violation.

Q8 : What steps we take while doing scan planning ?

Ans :
We have to decide the following :

• To check for which blocks compression is required (if a block is very small, we don’t require compression)

• no. of EDT channels and scan chains

• Shift frequency

Q9 : How will you create edt_clock and shift_capture clock ?

Ans :

Note :

• edt_clock is the clock which goes to the EDT logic flops.
  < < To understand EDT logic, please check out my DFT Basics Article #11 to 17 > >

• shift_capture_clock is the slow frequency clock of the scan flops.

The below structure creates shift_capture_clock

Image Source : Tessent Scan and ATPG User’s Manual

Let’s explore the above structure

Let’s explore the same using a waveform :

Similarly the below structure creates the edt_clock

Image Source : Tessent Scan and ATPG User’s Manual

Let’s explore the above structure

Q10: Why PD team require scandef file? What will happen if scandef file is not provided to the PD team?

Ans :

For scan chain re-ordering, PD team need scandef file because that file only contains information about which cells can be re-ordered.

If scandef file is not provided to PD team then, scan chain re-ordering can’t be done and it will result in congestion.

We have explored scan chain re-ordering in Scan Chain Re-ordering

References :
Tessent Scan and ATPG User’s Manual

In this blog post, we have explored some of the practical interview questions related to scan insertions and scan compression.
In the next blog of this series, we will explore some application oriented interview questions from ATPG.

Stay Tuned !

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