But I never really introduced why I started this newsletter or who I am. So here’s that overdue introduction 👇

I’m Kumar Ankit, a DFT VLSI engineer with experience at Synopsys, Intel, Qualcomm, and STMicroelectronics. Over the years, I've interacted with hundreds of students and professionals who want to enter VLSI but aren't sure where to begin. That’s where this newsletter comes in.

🎯 Why This Newsletter Exists

If you’ve ever wondered:

• Which tools should I learn first?

• Front end, back end, or DFT: which path is right for me?

• Is Verilog enough, or should I learn SystemVerilog too?

• What projects actually help me get interviews?

• How do I build a VLSI resume that stands out?

• What does a VLSI engineer actually do every day?

You're not alone. These inspired me to start VLSI with Ankit - a space where I break down complex VLSI fundamentals into clear, beginner-friendly insights, and offer direction for building a strong skill foundation; based on my experience.

🔍 What You’ll Get Here:

• Beginner-friendly explanations of Verilog, DFT, STA, RTL Design, and more.

• Step-by-step learning roadmaps for different VLSI domains.

• Practical project ideas to strengthen your resume.

• Career advice, interview tips, and insights from the semiconductor industry.

This is everything I wish I’d known early on in my VLSI journey.

💼 Connect & Learn:

• Continue the conversation on LinkedIn - where I post VLSI updates, tool tips, and career advice (15K+ followers and growing).

• Need personalized help or guidance? Book a mentoring session through Topmate - offering VLSI career guidance, resume reviews, interview prep, and more.

Thanks for stopping by. Let’s build your chip design journey together.

Let’s compare them clearly and practically.

📌 First, What Are They?

FPGA (Field Programmable Gate Array) → a reconfigurable chip used for prototyping

ASIC (Application Specific Integrated Circuit) → a customized chip for a specific product

📌 Key Differences (Simple Comparison)

📌 Where They Are Used

• FPGA Applications: 5G testing, aerospace, automotive, robotics, AI accelerators

• ASIC Applications: Smartphones, CPUs, GPUs, modems, SoCs, sensors

📌 Which One Should You Learn First?

✅ Short answer: Start with FPGA, then move to ASIC.

Why?

📌 Skill Path: FPGA → ASIC

If you’re serious about VLSI, here’s a simple learning roadmap:

1. Learn Verilog/SystemVerilog

2. Simulate designs (ModelSim, EDA Playground)

3. Implement on FPGA (Vivado)

4. Learn Synthesis + PnR basics

5. Move to ASIC timing (STA), DFT, PD

📌 Interview Reality

Both domains value RTL + logic design + timing. FPGA gives you a practical start without expensive tools.

📌 Final Advice

If you’re just starting your journey:

✅ Begin with FPGA to build confidence
➡ Then move into ASIC for deeper VLSI specialization

You don’t have to choose one forever. Many engineers start in FPGA and transition to ASIC easily.

📌 What is a MOSFET?

A MOSFET is an electronic switch that controls the flow of current using an electric field. It has three terminals (four in real design):

Think of it like a water tap:

• Source = Tank

• Drain = Pipe exit

• Gate = Tap handle (controls flow)

  

  Image Source : https://www.mks.com/n/mosfet-physics

📌 Types of MOSFETs

Both NMOS and PMOS work together in CMOS logic.

📌 How a MOSFET Works (Simple Idea)

When voltage is applied to the Gate, it creates an electric field through the oxide, forming a channel between Source and Drain:

No Gate Voltage → No channel → MOSFET OFF

Gate Voltage Applied → Channel created → MOSFET ON

In an NMOS, current flows when Vgs > Vth
In a PMOS, current flows when Vgs < Vth

📌 Why MOSFETs Matter in VLSI

Every logic gate, flip-flop, buffer, and cell in a chip is built using MOSFETs.

📌 Real-World Visual: CMOS Inverter = 2 MOSFETs

A CMOS inverter is just:

• 1 PMOS (pull-up to VDD)

• 1 NMOS (pull-down to GND)

Input goes to both gates → Output flips accordingly.

This tiny blueprint scales into millions of gates in your CPU!

📌 Key MOSFET Terms to Know

Vth → Threshold voltage

IdsDrain → source current

W/L → Channel width & length

Cgs/Cgd → Gate capacitances

Ion/Ioff → On/off current

📌 Quick Intuition Check
✅ Why is PMOS placed at the top?
→ Because it passes strong ‘1’ better.
✅ Why does NMOS sit at bottom?
→ Because it passes strong ‘0’ better.

📌 Resources to Learn MOSFETs (Visual First)

• Simulate a MOSFET in LTSpice or Ngspice

• Introduction to MOSFET by Behzad Razavi :

• Book: CMOS VLSI Design by Weste & Harris (Chapter 2)

💬 Final Thought
You don’t truly understand digital design until you understand MOSFETs.
Learning them visually builds the intuition you’ll need for timing, STA, power analysis, and CMOS design.

📌 What is Verification?
Verification is the process of ensuring the design matches the specification — before fabrication.

• Uses simulation, formal methods, and emulation

• Catches functional bugs in RTL or gate-level design

• Typical outputs: Testbenches, coverage reports, bug reports

Analogy: Verification is like proofreading a document before you print it — you fix typos before wasting paper.

📌 What is DFT?
Design for Testability focuses on ensuring the chip can be tested after fabrication.

• Adds structures like scan chains and BIST (Built-In Self-Test)

• Detects manufacturing defects (shorts, opens, stuck-at faults)

• Uses ATPG patterns and high-speed testers on real silicon

Analogy: DFT is like adding an inspection checklist for every copy of the printed document to make sure no pages are missing or ink is smeared.

📌 Key Differences

📌 Why Both Matter
Skipping verification means you risk taping out a broken design.
Skipping DFT means you risk shipping faulty chips to customers.
Both are essential for a reliable VLSI product.

📌 Career Insights

• Verification roles are ideal if you love coding, debugging, and system-level thinking.

• DFT roles suit engineers interested in test architectures, manufacturing processes, and hardware-software interaction.

Some engineers even transition between the two, as both require logical thinking and design knowledge.

💡 Pro Tip:
Understanding both domains makes you more versatile. Even as a verification engineer, knowing DFT helps you write testbenches that account for scan mode. As a DFT engineer, knowing verification helps in validating your inserted structures.

How does verification vs DFT thinking differ?

Verification : Does AND gate output correct logic (A&B)?

DFT : Can I test each flop for defects via scan chain?

📌 What Is a Netlist?

A netlist is a text-based representation of a digital circuit.
It describes:

• Components (gates, flip-flops, macros, etc.)

• Connections (wires or “nets”) between those components

It’s like the blueprint of your design after RTL has been synthesized.

📌 Types of Netlists

There are several forms of netlists, depending on the design stage:

📌 Sample Netlist Snippet

module AND2 (input A, B, output Y);
assign Y = A & B;
endmodule

// After synthesis
AND2_X1 U1 ( .A(a), .B(b), .Y(y) );

This shows an instance U1 of a 2-input AND gate connecting inputs a and b to output y.

📌 Why Is the Netlist So Important?

• Debugging: You can trace signal paths and logic errors.

• Place & Route: Used by physical design tools for layout.

• Timing Analysis: Essential input for STA tools.

• Power Estimation: Used in power analysis with real net connectivity.

• DFT: ATPG tools use netlist for scan chain generation.

📌 Real-World Applications

• During synthesis, your HDL code (Verilog/VHDL) gets transformed into a gate-level netlist.

• During signoff, the netlist + parasitic data is used for accurate analysis.

📌 Pro Tip for Freshers

Understanding how to read a netlist will help you debug synthesis issues, timing failures, or even physical design congestion — even if you’re not a backend engineer.

“If RTL is the ‘idea,’ the netlist is the actual implementation plan.”

If you're in your 2nd or 3rd or final year of B.Tech or 1st year of M.Tech and dream of landing a core VLSI job, this post is for you.

📌 Step 1: Know What VLSI Roles Look Like

Before you prepare, understand what you're preparing for. VLSI companies hire for various domains:

• RTL Design

• DFT (Design for Testability)

• Physical Design

• Verification (Functional/Formal)

• Analog/Mixed-Signal Design

• Timing Analysis (STA)

📝 Pro Tip: Don’t aim to learn everything. Pick 1-2 roles that excite you and build depth in that area.

📌 Step 2: Master the Core Subjects

These are the foundation of any VLSI placement preparation:

👉 Bonus: Learn basics of DFT or PD to stand out in interviews — very few students touch these.

📌 Step 3: Build Hands-on Skills

Companies don’t just want theory — they want implementation!

✅ Do these:

• Create simple RTL projects (counters, ALUs, UART, etc.)

• Use tools like EDA Playground or Vivado

• Simulate and debug testbenches

• Explore Open-source tools: Xilinx ISE, Icarus Verilog, Yosys, etc.

🎯 Pro Tip: Document your projects well — GitHub + LinkedIn + Substack summaries can massively boost visibility.

📌 Step 4: Resume that Speaks Silicon

What to include:

• VLSI-specific skills (Verilog, STA, DFT, etc.)

• Mini-projects with quantifiable outcomes

• Internships or online certifications (NPTEL, Udemy)

• GitHub / LinkedIn profile link

🚫 Avoid:

• Generic resume buzzwords ("team player", "hardworking")

• Too many non-VLSI unrelated projects

📌 Step 5: Crack the Written + Interview Rounds

Written Tests may include:

• Aptitude (quant + logical)

• Digital basics

• Verilog coding snippets

• Some C programming or puzzles

Interview Prep Checklist:

• Be clear with CMOS inverter & SRAM basics

• Can you write a 2:1 Mux in Verilog?

• Know setup vs hold timing violations

• Explain your project end-to-end

🎤 Mock interviews with friends or seniors can be game-changing.

📌 Step 6: Use the Right Resources

Books:

• Digital Design – Morris Mano

• CMOS VLSI Design – Weste & Harris

• Verilog HDL – Samir Palnitkar

Courses:

• NPTEL Digital IC Design – Prof. Janakiraman

• VSD (VLSI System Design) online platforms

• LinkedIn Learning or Udemy for tool exposure

Practice:

• EDA Playground (free RTL simulations)

• Hackerrank/GeeksForGeeks for C and aptitude

📌 Final Advice: Prepare Early, Showcase Smartly

“Don’t wait for companies to arrive — build yourself before they knock.”

• Start in 5th or 6th semester or even earlier, not final year panic mode.

• Post your learning journey on LinkedIn.

• If you don't get a dream core job on Day 1, don’t lose hope — VLSI is a long game.

Keep learning. Keep building.

I regularly share VLSI insights, industry updates, and career tips.
🔗 LinkedIn: Kumar Ankit

“Do I really need to study Basic Electrical Engineering (BEE) for a career in VLSI?”

The short answer? Not everything, but yes — the essentials matter.

📌 The Quick Answer
You don’t need to master electrical machines or power systems. But a strong grasp of basic electronics and circuit fundamentals is absolutely crucial for success in VLSI.

📌 Why Electrical Engineering Basics Still Matter?
Even though VLSI aligns more with electronics than heavy electrical engineering, these fundamentals form the foundation of everything you’ll do later in RTL, STA, or DFT:

• How transistors switch (CMOS basics)

• Why signals get delayed (RC delay models)

• What causes glitches or timing violations

• How power is consumed and optimized in circuits

If you skip this layer, high-level tools and languages can feel like black boxes.

📌 What You Don’t Need to Go Deep Into?
Don’t waste time worrying about topics like:

• Power systems (3-phase supply, motors, generators)

• High-voltage engineering

• Electrical machine design

These are not relevant in a mainstream VLSI career (unless you move into power ICs or analog mixed-signal).

📌 What to Focus On Instead?
If you’re preparing for VLSI placements or internships, focus on electronics concepts that directly translate into digital design:

• CMOS basics (pull-up/pull-down, noise margin)

• Combinational & sequential circuits

• Flip-flops, latches, counters

• Timing (setup, hold, skew, etc.)

• Boolean algebra & logic gates

• FSMs (finite state machines)

Supplement this with:

• RC delay models

• Static and dynamic power basics

• Layout concepts (vias, metal layers, parasitic capacitances)

📌 Projects to Reinforce Concepts
Hands-on practice is the fastest way to connect BEE to VLSI:

• Design a CMOS inverter and measure delays in SPICE

• Simulate a 4-bit ripple counter in Verilog

• Build a mini-ALU on an FPGA board

• Analyze signal delay/power trade-offs using LTspice

📌 Recommended Resources

• Book → Microelectronic Circuits by Sedra/Smith (relevant chapters only)

• NPTEL → Introduction to Electrical Engineering, IIT Delhi

• Basic Electrical Circuits, IIT Madras

• Tools → LTSpice (analog sim), Digital by HILEY (logic circuits)

📌 Final Thoughts
Basic Electrical Engineering isn’t a full prerequisite, but the right parts of it will make you a stronger VLSI engineer.

• It helps you debug timing reports with confidence

• It makes sense of power issues in design

• It builds intuition for what’s really happening inside those “black box” gates

Master the essentials. Skip the irrelevant. Build the foundation that makes you stand out in VLSI interviews and jobs.

📌 Why Care About Semiconductor Devices in VLSI?

• They’re the real hardware behind every logic gate you design

• They control delay, power, and area — the heart of STA and PnR

• CMOS = NMOS + PMOS → knowing how they switch is essential

• A solid device-level grasp helps in RTL, STA, DFT, layout, and beyond

Interactive check:
When you see a timing violation in STA, what’s the root cause?
(a) Bad Verilog
(b) Slow transistors
(c) Wrong synthesis tool
(Answer: often b — device behavior!)

📌 What Is a Semiconductor Device?

A semiconductor is a material (like silicon) whose conductivity lies between conductors (like copper) and insulators (like glass). By adding small amounts of impurities (a process called doping), we can create:

• N-type regions (extra electrons)

• P-type regions (extra holes)

These become the foundation of transistors — particularly the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which is the fundamental building block of digital VLSI.

📌 CMOS Technology: Where It All Comes Together

In digital VLSI, we predominantly use CMOS (Complementary MOS) technology — which combines NMOS and PMOS transistors in pairs.

Why CMOS?

• Low static power (no DC current when idle)

• Scalable & reliable for fabs

• Noise-immune, high performance

Every logic gate, from NOT to XOR, is built using CMOS transistors. At the heart of each? The humble inverter.

📌 Example: The CMOS Inverter

A CMOS inverter has:

• One PMOS at the top (pull-up)

• One NMOS at the bottom (pull-down)

This switching is the foundation of digital logic. And the delay, power, and noise behavior of this inverter depends entirely on the semiconductor physics behind those transistors.

📌 Why Semiconductor Devices Matter in VLSI Jobs

Whether you’re going into front-end RTL or back-end layout, here’s why a strong grasp on devices pays off:

• Timing: Delay through gates depends on transistor switching speed

• Power: Leakage and dynamic power are both device-level phenomena

• Area: PMOS/NMOS sizing impacts standard cell footprint

• Reliability: Threshold shifts, short-channel effects, and leakage are all tied to physical properties

Knowing how these devices behave lets you:

• Interpret synthesis results more meaningfully

• Debug STA reports faster

• Optimize layout with better transistor sizing decisions

📌 Quick Reference: NMOS vs PMOS

📌 How to Learn Semiconductor Devices (Without Getting Overwhelmed)

You don’t need to become a device physicist. But you do need to understand basic principles like:

• Threshold voltage (Vth)

• On/Off current (Ion/Ioff)

• Channel length and width

• Drain current equations

Recommended Learning Resources:

• CMOS VLSI Design by Weste & Harris

• NPTEL – Semiconductor Devices or Digital IC Design

• Tools: Simulate inverter behavior using LTspice or Ngspice

• Optional: Use Sky130 PDK and Xschem for real transistor-level designs

📌 Final Thoughts

Every register, NAND gate, buffer, or scan chain is just an arrangement of transistors. The better you understand how MOSFETs behave, the stronger your foundation in any VLSI role — RTL, STA, DFT, layout, or verification.

I regularly share VLSI insights, industry updates, and career tips.
👉 linkedin.com/in/kumar-ankit

In this issue of the “VLSI by Ankit” newsletter, we’ll walk through how to design a 4-bit ALU (Arithmetic Logic Unit) in Verilog, and simulate it with a testbench. If you’re just starting with RTL design or digital logic, this is a must-do project to solidify your understanding.

📌 What’s an ALU?

An ALU is a digital circuit that performs arithmetic and logic operations. It’s a key component in processors, from microcontrollers to advanced CPUs.

A basic 4-bit ALU typically supports:

• Addition (A + B)

• Subtraction (A - B)

• AND (A & B)

• OR (A | B)

• XOR (A ^ B)

• NOT (~A)

• Increment/Decrement

• Compare operations

📌 Verilog Code for 4-Bit ALU

module ALU_4bit (
    input  [3:0] A,
    input  [3:0] B,
    input  [2:0] opcode,
    output reg [3:0] result,
    output reg carry
);
    always @(*) begin
        case(opcode)
            3'b000: {carry, result} = A + B;       // Addition
            3'b001: {carry, result} = A - B;       // Subtraction
            3'b010: result = A & B;                // AND
            3'b011: result = A | B;                // OR
            3'b100: result = A ^ B;                // XOR
            3'b101: result = ~A;                   // NOT A
            3'b110: result = A + 1;                // Increment A
            3'b111: result = A - 1;                // Decrement A
            default: result = 4'b0000;
        endcase
    end
endmodule

📌 Testbench to Simulate It

module tb_ALU_4bit;
    reg [3:0] A, B;
    reg [2:0] opcode;
    wire [3:0] result;
    wire carry;

    ALU_4bit alu (.A(A), .B(B), .opcode(opcode), .result(result), .carry(carry));

    initial begin
        $display("Opcode | A  | B  | Result | Carry");
        A = 4'b0101; B = 4'b0011;

        opcode = 3'b000; #10; // Add
        $display("  ADD  | %b | %b |  %b   |  %b", A, B, result, carry);

        opcode = 3'b001; #10; // Sub
        $display("  SUB  | %b | %b |  %b   |  %b", A, B, result, carry);

        opcode = 3'b010; #10; // AND
        opcode = 3'b011; #10; // OR
        opcode = 3'b100; #10; // XOR
        opcode = 3'b101; #10; // NOT A
        opcode = 3'b110; #10; // INC A
        opcode = 3'b111; #10; // DEC A

        $finish;
    end
endmodule

📌 Simulation Output

Expect outputs like:

Opcode | A    | B    | Result | Carry
  ADD  | 0101 | 0011 | 1000   | 0
  SUB  | 0101 | 0011 | 0010   | 0
  AND  | 0101 | 0011 | 0001   | 0
  OR   | 0101 | 0011 | 0111   | 0
  XOR  | 0101 | 0011 | 0110   | 0
   …   

📌 Why This Project Matters

• It introduces Verilog constructs like always @(*), case, and modules

• Gives you hands-on understanding of arithmetic/logic operations

• It’s a mini-processor component — great for portfolio or interviews

📌 Extend It!

• Add more operations like multiplication or shift

• Make a 16-bit version

• Add flag outputs: Zero, Negative, Overflow

• Try synthesizing it using a tool like Vivado or Quartus

Building a 4-bit ALU is like a rite of passage for every digital designer. Once you’ve done it, you’re one step closer to understanding how CPUs work under the hood.

📌 What Is RTL?

Register Transfer Level (RTL) describes a digital circuit in terms of how data moves between registers and the operations performed on that data.

At this level, you use HDLs (Verilog/VHDL) to express logic that is:

• Structured

• Timing-aware

• Synthesizable

Put simply, RTL is how designers tell silicon what to do.

📌 What RTL Includes:

• Registers (flip-flops or latches): For storing data

• Combinational logic: For processing or computing

• Control logic: For deciding when and how data moves

• Clocking and reset logic

At this level, you define:

• What data moves

• When it moves

• Where it moves to

📌 Why RTL Matters

✅ It’s the level you use in job interviews and real-world design
✅ RTL code is synthesizable — meaning tools can convert it to gates
✅ It allows for early simulation and debugging
✅ It’s the backbone of DFT, timing analysis, power optimization, and more

📌 A Simple RTL Example (Verilog)

module counter (
    input clk,
    input rst,
    output reg [3:0] count
);
always @(posedge clk or posedge rst) begin
    if (rst)
        count <= 0;
    else
        count <= count + 1;
end
endmodule

This is a classic RTL example:

• Uses clock and reset

• Updates register (count) on posedge

• No delays or high-level behavioral constructs

📌 RTL vs Behavioral vs Gate-Level

📌 Tips to Master RTL as a Fresher

• Start writing simple Verilog modules: muxes, ALUs, counters, FSMs

• Understand synchronous design and blocking vs non-blocking assignments

• Use EDA tools like Vivado, ModelSim, or GHDL

• Read RTL code from open-source projects or GitHub

• Always simulate before synthesizing!

Mastering RTL early is like learning the grammar of digital design — it’s the foundation on which every VLSI engineer builds.

📌 Myth #1: "VLSI has no scope in India"
✅ Truth: India is becoming a hotspot for VLSI.

• Intel, Qualcomm, AMD, Mediatek, Samsung, and Google all have large teams here.

• With the India Semiconductor Mission (ISM) and new fabs like Tata-Micron, opportunities are only growing.

It’s not about “scope,” it’s about whether you’ve built the right skills.

📌 Myth #2: "You must be a topper or IITian to get into VLSI"
✅ Truth: Not true at all.
Engineers from Tier 2/3 colleges have landed core jobs by:

• Learning the right tools and concepts

• Building projects

• Showcasing their work on GitHub/LinkedIn

Companies hire based on skill + attitude, not just college brand.

What matters more: Can you write Verilog? Can you debug timing issues?

📌 Myth #3: "VLSI = only front-end coding in Verilog"
✅ Truth: VLSI has a huge ecosystem:

• Front-End: RTL design, verification, DFT

• Back-End: Physical design, STA, layout

• Post-Silicon: Testing, validation

• EDA Development: Tools from Cadence, Synopsys, Siemens

• FPGA, Emulation, IP Integration

Coding is important, but it’s just one part of the puzzle.

📌 Myth #4: "You can’t get into VLSI without M.Tech or specialization"
✅ Truth: Many engineers start right after B.Tech.
An M.Tech in VLSI or Microelectronics helps, but it’s not mandatory.

Focus on:

• Learning Verilog/SystemVerilog

• Doing 1–2 solid projects

• Understanding tools like ModelSim, Genus, DFT Compiler, Vivado

📌 Myth #5: "Only big companies like Intel or Qualcomm hire VLSI engineers"
✅ Truth: There are hundreds of smaller and mid-sized companies actively hiring:

• EDA companies: Cadence, Synopsys, Siemens EDA

• Product startups: Invecas, Terminus Circuits, Saankhya Labs

• Service-based firms: Sankalp, Tessolve, Wipro VLSI, HCL

And here’s the kicker: these smaller firms are often where you learn the most early in your career.

Final Thought
Don’t let myths hold you back from a high-impact, high-growth career in VLSI.

Start small. Learn one tool. Build one project. Share your learning. The opportunities will follow.

📌 Why This Matters

If you're building FSMs, timing models, or writing RTL in Verilog, you need to understand when and why to use a latch vs a flip-flop.

It’s one of the most asked interview questions, and yet, a surprisingly misunderstood topic.

Let’s break it down — clearly, visually, and practically.

The Core Difference

💡 Think of it like this:

• A latch is like an open gate — data keeps flowing as long as the enable is active.

• A flip-flop is like a camera shutter — it takes a snapshot only at a specific instant (the clock edge).

SR Latch → D Latch → D Flip-Flop

Let’s quickly look at how things evolved:

1. SR Latch: Basic storage unit using NOR/NAND gates.

2. D Latch: Simplifies control with a single input. Stores data while enable is active.

3. D Flip-Flop: Adds edge-triggering, eliminating transparency issues in clocked systems.

Timing Perspective

• Latch Transparency: If not used carefully, can introduce glitches or race conditions.

• Flip-Flops introduce setup and hold timing constraints, but are predictable and safer for synthesis.

Pro Tip:
Most modern synthesis tools infer flip-flops, and avoid level-sensitive latches due to timing complexity.
However, latches still have use in low-power paths, clock gating, and custom analog-mixed signal designs.

👨‍💻 Representation and Timing Diagram

RTL Coding Example

❌ Bad latch-style coding (can infer unintended latches):

always @(enable or d)
  if (enable)
    q = d;

✅ Proper flip-flop style:

always @(posedge clk)
  q <= d;

Interview Takeaways

1. Know when transparency is good vs dangerous.

2. Be able to draw timing diagrams.

3. Use flip-flops unless you're doing power optimization or analog-heavy design.

4. Always mention this clearly in RTL questions if latches are brought up.

5. In DFT, latches require extra care during scan chain insertion.

📌 Final Thought

“Every flip-flop was once a latch that got disciplined by the clock.”

If you’ve ever been confused about the difference — now you know. Save this post, and maybe even use it in your next seminar or peer session.

In this issue of the “VLSI with Ankit” newsletter series, let’s demystify what actually goes on inside your smartphone’s processor. You’ve heard of Snapdragon, A-series, or MediaTek chips — but what’s really inside these powerful pieces of silicon?

What Is a Smartphone SoC?

An SoC (System-on-Chip) is an integrated circuit that combines multiple functions onto a single chip — it’s essentially the brain of your phone.

A modern SoC includes:

• Central Processing Unit (CPU)

• Graphics Processing Unit (GPU)

• Image Signal Processor (ISP)

• Neural Processing Unit (NPU)

• Digital Signal Processor (DSP)

• Modem (for 4G/5G)

• Memory controllers

• Secure Enclave

• Power Management Units (PMUs)

Key Components & Their VLSI Role

A Visual Breakdown (Simplified)

Every block above is the result of a massive VLSI effort — involving RTL design, synthesis, STA, floorplanning, DFT insertion, verification, and physical layout.

What VLSI Engineers Do in SoC Design

• Front-End Engineers: Write RTL for CPUs, NPUs, etc.

• Verification Engineers: Ensure correct functionality (UVM/Assertions)

• DFT Engineers: Add scan chains, BIST to test the chip post-fabrication

• Backend Engineers: Place, route, and optimize timing/power/area

• Physical Verification: Ensure DRC/LVS compliance before tape-out

Did You Know?

• A flagship SoC may contain 10–15 billion transistors

• It's built using 5nm or even 3nm technology

• Each chip goes through millions of STA and DRC checks

• Power management is so refined that it shuts off unused blocks in nanoseconds!

Why This Matters for VLSI Aspirants

Understanding SoC internals helps you:

• Know where your VLSI skills apply

• See the big picture in chip design

• Pick a specialization: CPU vs DSP vs DFT vs STA

💡 Final Thoughts

Your smartphone isn’t just “fast” — it’s a masterclass in VLSI engineering.

Next time you unlock your phone, remember: you’re holding billions of gates, thousands of clock domains, and years of engineering effort — all in your palm.

Whether you're preparing for campus placements or starting your first VLSI internship, these practical tips will save you from hours of debugging and confusion.

Mistake #1: Mixing Blocking and Non-Blocking Assignments

Many learners use = and <= interchangeably.
Tip:

• Use = for combinational logic (in always @*)

• Use <= for sequential logic (in always @(posedge clk))

Mistake #2: Ignoring Reset Conditions

Skipping reset logic can lead to unpredictable simulations and synthesis issues.
Tip:
Always define an async/sync reset path in your sequential blocks.

Mistake #3: Using Delays (#) in RTL Code

While delays might work in simulation, they’re not synthesizable.
Tip:
Don’t use #10 or any timing control in synthesizable RTL. Use clock-driven events instead.

Mistake #4: Overusing initial Blocks

initial blocks are meant for testbenches, not synthesizable logic.
Tip:
In RTL design, replace initial with reset logic.

Mistake #5: Poor Module/Testbench Structure

Writing everything in one file or mixing testbench with RTL is messy.
Tip:
Separate RTL and testbench files. Keep your code modular and readable.

Bonus Tip:

Comment your code and use descriptive signal names. This helps you and your future team when reviewing or debugging code.

📌 4-Bit ALU (Arithmetic Logic Unit)
Design an ALU that performs operations like addition, subtraction, AND, OR, and XOR.

• Key Skills: Combinational logic, case statements, testbench writing

• Bonus: Add overflow detection and zero flag output

📌 Traffic Light Controller
A simple finite state machine (FSM) to control traffic signals.

• Key Skills: Sequential logic, FSM design, timing simulation

• Bonus: Implement a pedestrian crossing mode

📌 Binary to BCD Converter
Convert binary numbers to BCD format for display purposes.

• Key Skills: Algorithm implementation in HDL, shift-and-add method

• Bonus: Drive a 7-segment display in simulation

📌 Sequence Detector
Detect a specific bit pattern in a serial input stream (e.g., “1011”).

• Key Skills: Mealy vs Moore FSM, state transition diagrams

• Bonus: Make it parameterized so you can change the sequence easily

📌 Simple UART Transmitter/Receiver
Send and receive serial data at a fixed baud rate.

• Key Skills: Timing generation, shift registers, async communication

• Bonus: Add parity bit support

📌 PWM Generator
Generate a Pulse Width Modulated signal to control devices like motors or LEDs.

• Key Skills: Counters, duty cycle control

• Bonus: Make the duty cycle adjustable via inputs

📌 Digital Stopwatch
Count time in seconds and minutes, with start, stop, and reset controls.

• Key Skills: Counters, multiplexing, debouncing inputs

• Bonus: Display output on a simulated 7-segment display

💡 Pro Tip:
Keep your projects modular — split them into smaller Verilog modules and connect them at the top level. This makes debugging and testing much easier, and it’s exactly how industry projects are structured.

This is one of the most asked questions I get from students and early-career engineers:

Should I go into Analog Design or Digital Design?

Let’s break it down — clearly and practically — so you can make a confident choice.

📌 What is Analog Design?

Analog design is all about continuous-time signals — voltage and current that vary smoothly and are affected by noise, parasitics, temperature, and layout effects. You're working close to the physics of the transistor.

Typical Roles:

• Analog Circuit Designer

• RF or Mixed-Signal Design Engineer

• AMS Verification Engineer

Key Work Includes:

• Designing op-amps, ADCs, PLLs, etc.

• Running SPICE simulations

• Tuning circuits for gain, bandwidth, noise, and stability

• Working closely with layout teams

📌 What is Digital Design?

Digital design revolves around discrete logic levels — 0s and 1s. It’s about how data flows, how operations happen in sync with the clock, and how the entire chip works logically.

Typical Roles:

• RTL Design Engineer

• Functional/DFT Verification Engineer

• Physical Design Engineer

• STA (Static Timing Analysis) Engineer

Key Work Includes:

• Writing and debugging Verilog/VHDL code

• Synthesizing and simulating logic

• Ensuring timing closure

• Verifying functionality through testbenches or ATPG

📌 Analog vs Digital – What’s the Real Difference?

📌 Which One Should You Choose?

Ask yourself these questions:

✅ Choose Analog Design if:

• You enjoy circuit theory, EDC, and device physics

• You like low-level details, precision, and layout constraints

• You want to work in smaller, niche teams with deep specialization

✅ Choose Digital Design if:

• You enjoy logic design, coding, and debugging

• You like system-level thinking and scalable design flows

• You want flexibility to move between DFT, verification, or even embedded roles

📌 Skills You’ll Need

Analog Path:

• CMOS device physics, small-signal models

• Op-amps, filters, biasing techniques

• SPICE simulation (Cadence/Spectre)

• Layout knowledge (matching, shielding, routing)

Digital Path:

• Verilog or VHDL (RTL design)

• FSMs, timing analysis, synthesis

• Functional & formal verification

• EDA tools: Synopsys, Cadence, Siemens

📌 Recommended Resources

Analog

• Book : Design of Analog CMOS Integrated Circuits by B. Razavi

• Electronics Lecture Series by Razavi

• Simulators like Cadence Virtuoso and LTSpice

• NPTEL Analog Electronics IIT Madras by Prof Shanthi Pavan

• NPTEL Analog Electronics IIT Delhi

• Series by Neso Academy (Short Videos for Quick Revision)

• Lecture Series by Umesh Dhande (India’s GATE Exam perspective)

  
  

Digital

• Resources can be found in this post : Digital Electronics Ankit Substack

📌 Final Thoughts

Both analog and digital design are foundational pillars of the semiconductor world.

Choose what aligns best with your interest, learning style, and career vision. Try both if you're unsure — student projects, internships, and simulations are the best ways to explore!

You don't have to decide forever — many engineers eventually transition to mixed-signal roles or broaden across domains.

Whether you're writing your first Verilog module or preparing for a campus placement interview — understanding this difference is fundamental.

📌 What Are Combinational Circuits?

A combinational circuit is a type of digital circuit where the output only depends on the current inputs — there’s no memory or storage involved.

Key Features:

• No clock or flip-flops

• Output changes immediately with input

• Pure logic — adders, multiplexers, decoders, etc.

Examples:

• Half Adder / Full Adder

• Multiplexers (MUX)

• Encoders / Decoders

• ALU blocks (arithmetic parts)

Truth Table-Based Design:

Designing combinational circuits usually starts from a truth table, followed by:

• Boolean expressions

• Logic simplification (K-maps)

• Gate-level implementation

📌 What Are Sequential Circuits?

Sequential circuits have memory. The output depends on current inputs + past history, usually stored using flip-flops or latches.

Key Features:

• Uses clock signal

• Stores previous states

• Essential for timing-sensitive operations

Examples:

• Flip-Flops (D, JK, T)

• Counters

• Shift Registers

• Finite State Machines (FSMs)

Time-Driven Logic:

Sequential designs work in clock cycles, introducing concepts like:

• Setup and hold time

• Edge sensitivity

• Clock domains

📌 Comparison

Image Source : https://www.hackatronic.com/difference-between-combinational-and-sequential-circuits/

📌 Where Do You Use Each?

In real-world chips, both types are deeply intertwined.

• Combinational blocks are used for logic evaluation

• Sequential blocks bring timing and control into the system

In RTL design:

• Combinational logic handles data paths

• Sequential logic handles control logic and pipelining

📌 How to Master This as a Student

1. Build circuits like counters, ALUs, decoders

2. Simulate using Verilog (EDA Playground is great)

3. Learn to draw timing diagrams

4. Practice converting state diagrams to FSM code

📌 Suggested Resources

Books :

1. Digital Logic & Computer Design – M. Morris Mano
   A classic—deeper and slightly more theoretical, but a must-have reference.

   Doc Link

2. Modern Digital Electronics – R.P. Jain
   Especially useful in Indian university contexts. Simple and comprehensive.

Web Resources :

1. NPTEL : Lecture series on Digital Circuits & Systems by Prof.S.Srinivasan, Department of Electrical Engineering, IIT Madras.

   NPTEL Course Link
   

2. Neso Academy YouTube - Playlist Link (Mainly for quick revision, short videos)

Basic Simulations :

1. EDA Playground : Use here
   Try simple gate-level and RTL simulations with Verilog/SystemVerilog online.

📌 Final Thoughts

"If combinational logic is the brain, sequential logic is the heartbeat."

You’ll encounter these everywhere — in interviews, in RTL code, and in silicon. Master this early, and your digital design journey will become much smoother.

📌 What Is a Clock in Digital Design?

A clock is a repetitive signal—typically square-shaped—that coordinates the timing of operations in sequential circuits. Each rising or falling edge of the clock determines when data is sampled, stored, or transferred.

Fig : Representation of a clock pulse

📌 Combinational vs Sequential Logic

• Combinational logic doesn’t require a clock—it produces output purely based on current inputs.

• Sequential logic, like registers or flip-flops, requires a clock to control state transitions.

Without a clock, digital systems would behave erratically—much like trying to run a factory with no schedule!

📌 Why Clocking Matters in VLSI

• Data Synchronization: Ensures all parts of a chip operate in harmony.

• Timing Accuracy: Defines setup, hold, and propagation delays.

• Power & Performance Tradeoffs: Clock frequency impacts power consumption and speed.

• Design Closure: Clock paths are critical in STA (Static Timing Analysis) and CTS (Clock Tree Synthesis).

📌 Key Clock-Related Concepts to Know

• Clock Skew: When clock edges arrive at different components at slightly different times.

• Clock Jitter: Tiny variations in clock period that can lead to errors.

• Clock Gating: Technique used to reduce power by disabling the clock when not needed.

• Multicycle Paths: Paths that intentionally take more than one clock cycle.

📌 Real-World Applications

Whether you're designing a microprocessor, writing Verilog, or debugging a timing failure, everything revolves around the clock.

📌 How to Master It as a Student/Fresher

• Simulate flip-flops, counters, and FSMs in Verilog.

• Use waveform viewers like GTKWave to visualize clock-driven behavior.

• Dive into STA tools and understand timing reports.

If you're applying for RTL, DFT, PD, STA, or analog roles — your resume is the first gate you must pass. And it's where many get filtered out, even before the interview.

So let’s fix that.

📌 First: What Recruiters Really Look For

Recruiters don’t want a fancy resume. They want signal, not noise.

Here's what stands out:

• Relevant technical skills (Verilog, STA, DFT… not just C++)

• Clear project experience with outcomes

• Clean formatting (PDF, max 1 page for freshers)

• Evidence of genuine interest in VLSI (certificates, workshops, open-source tools)

📌 What to Include (And How)

1. Your Profile/Objective (Optional)

Bad: “I am a hardworking, sincere, dedicated student…”

Good: “VLSI-focused final-year student with hands-on RTL and DFT projects. Looking to contribute to front-end design and verification roles.”

2. Technical Skills

Separate into categories for clarity:

• Languages: Verilog, SystemVerilog, C

• Tools: ModelSim, Vivado, Design Compiler, Tessent, etc.

• Concepts: DFT, Synthesis, STA, CMOS

Tip: Tailor this list based on the job you're applying for then the concept section is not needed but would be understood as per the job.

3. Projects

Use this format:

• Title – Tool Used – Duration

• Short description (1-2 lines)

• Mention your role, what you learned, what was achieved

Include 2–3 solid projects. Even better if they match the domain you're targeting.

4. Education

Stick to the basics: Degree, College, CGPA, Duration

Include any coursework like but it is optional unless a certification is attained apart from the regular curriculum:

• Digital Design

• CMOS Design

• VLSI Systems

• DFT Techniques

5. Certifications / Online Courses

Mention only relevant ones:

• NPTEL Digital VLSI Design

• Udemy/LinkedIn courses on Verilog, Synopsys tools, etc.

Tip: Don’t list Online Courses you haven’t completed or understood.

6. Extra Sections (optional but useful)

• GitHub / LinkedIn / Substack portfolio

• Publications / Hackathons / Paper presentations

• Internships or on-campus lab work (even unpaid)

📌 What to Avoid

• Long, boring objectives

• Non-VLSI projects (unless exceptional)

• Word doc resumes (always submit as PDF)

• Fancy designs and colors

• Generic buzzwords (“good communicator”, “team player”, etc.)

📌 Quick Resume Tips Checklist

• Keep it to 1 page

• Save as YourName_VLSI.pdf

• Highlight tools, skills, projects

• Use bullet points, not paragraphs

• Proofread — one typing mistake can cost you which can show clumsiness or non-serious attitude

• Use consistent fonts and spacing

📌 Templates That Can Help You

One of the best minimal templates I found (and personally recommend) is this:

🔗 Wonsulting Resume Template – Shared via my LinkedIn

This format although dense is clean, and easy to customize for VLSI roles. Feel free to copy it and tweak it for RTL, DFT, Analog, or PD resumes.

💬 Final Thoughts

"Your resume isn’t your story. It’s your trailer. Make them want to see the full movie."

You don’t need a perfect GPA or 10 internships. You just need clarity, relevance, and proof of skills.

If you're still writing code on Windows, running Verilog in GUI-only tools, or dreading the command line — this post is for you.

📌 Why Linux Matters in VLSI

Most VLSI design environments - whether academic or industrial - run on Unix-based servers. That includes:

→ EDA Tools (Synopsys, Cadence, Mentor)
→ Simulation and Synthesis flows
→ Batch processing of netlists, test vectors, reports
→ Grid and cluster-based compute farms
→ Source control, scripting, and automation

In short: Linux is the invisible layer beneath almost everything in VLSI.

📌 Top Reasons to Learn Linux as a VLSI Engineer

1. EDA Tools are Optimized for Linux

Most industry-standard tools (Design Compiler, ICC2, Virtuoso, VCS, etc.) are natively supported on Linux.

2. You’ll Use the Terminal A Lot

VLSI work involves:

• Launching synthesis & simulations from terminal

• Editing files via vim or nano

• Navigating big hierarchies with cd, grep, find, etc.

• Running regression scripts and parsing logs

3. Scripting = Productivity

You’ll use:

• Shell scripting to automate runs and post-processing

• Perl/Python/Tcl to write tool interfaces

• Cron jobs to schedule long simulations or regressions

4. Servers Don’t Run Windows

Remote access to tool servers is done via:

ssh username@eda-server

You must be comfortable navigating headless systems.

5. Git, Makefiles, and Project Builds

Version control + flow automation often live in Linux pipelines. Understanding .bashrc, Makefile, .gitignore, and environment variables is a must.

📌 Basic Linux Skills to Master

📌 Practice Ideas for Students

1. Set up Ubuntu or use WSL (Windows Subsystem for Linux)

2. Use EDA Playground + terminal-based tools

3. Write a shell script to:

• Simulate a Verilog file

• Rename and move simulation logs

• Archive reports into .tar.gz format

4. Try editing a .lib or .sdf file using vim

📌 Resources to Learn Linux (VLSI-focused)

• NPTEL : Linux Programming & Scripting by Anand Iyer,Director, Calypto Design Systems.

• The Linux Command Line – William Shotts : Link

• Basic Commands

• Tool Practice: Try open-source tools like GTKWave, Icarus Verilog, Yosys — all run on Linux!

📌 Final Thoughts

“Linux is not just an OS — it’s your lab bench, microscope, and notebook all rolled into one.”

The sooner you get comfortable with Linux, the faster your productivity, confidence, and career-readiness will grow.

You don’t need to become a sysadmin — but you do need to be better than average at the terminal.